Datasheet TB9M001FTG (Toshiba) - 8
| 制造商 | Toshiba |
| 描述 | Automotive IC for DC motors with integrated microcontroller |
| 页数 / 页 | 38 / 8 — Preliminary. 9.2. LINPHY. 9.2.1 LINPHY Block Diagram |
| 文件格式/大小 | PDF / 4.9 Mb |
| 文件语言 | 英语 |
Preliminary. 9.2. LINPHY. 9.2.1 LINPHY Block Diagram
该数据表的模型线
文件文字版本
Preliminary
TB9M001FTG
9.2. LINPHY
Single responder-only LIN Phy channel Compliant with the ISO 17987-4, ISO 17987-7 12 V electrical physical layer (EPL), and SAE J2602 standards Withstands an ESD of ±6 kV (IEC 61000-4-2:2008, contact discharge, 150 pF, 330 Ω) Output slope control to reduce conducted EMI noise Programmable slew rate (Low Slope mode<10kbps>, Normal Slope mode<20kbps>, Fast Baud Rate mode<250kbps>) The values enclosed in < > indicate approximate baud rates. The figures enclosed between parentheses above are estimated baud rates. Output driver with a current limiter Thermal shutdown (TSD) circuit in the vicinity of the output driver A circuit that detects a wake-up request pulse from the LIN bus and notifies a system controller, PMU, etc. of the wake-up request Maximum pulse width of a wake-up request: 150 µs as specified by the LIN Specification The system control er, PMU, and other components perform the wake-up process upon receiving this notification, transition from low-power mode to Active mode, and issue an interrupt request to the CPU. W akeUp LPF Wake Up VB APB 30kΩ LPF WakeUp RXD ctrl. LIN Receiver UART Curr.Limit Slope Ctrl. Dominant TXD Timeout TSD Timer LIN ctrl. Transmitter LINGND normal/sleep
9.2.1 LINPHY Block Diagram
© 2 025 8 2025-05-30 Toshiba Electronic Devices & Storage Corporation Rev. 1.0 Document Outline 1. Description 2. Applications 3. Features 4. Functions 5. Block Diagram 6. Pin Assignments 7. Pin Description 8. I/O Equivalent Circuits 9. Functional Description 9.1. CPU 9.1.1. Overview 9.1.2. Arm® Cortex®-M0 Processor 9.1.3. Configurable Options 9.1.4. External Signals 9.1.5. Module Organization 9.2. LINPHY 9.3. LINCNT/UART1 9.4. SPI 9.4.1. External Signals 9.5. GPIO 9.6. 10bit Analog Digital Converter (GADC) 9.7. Low Side Drivers (LSD) 9.8. High Side Drivers (HSD) 9.9. High Voltage Inputs (HVIF) 9.10. Memory Map 10. Electrical Characteristics 10.1. Absolute Maximum Ratings 10.2. Operating Ranges 10.3. Overall Electrical Characteristics 10.4. 5-V/1.5-V Regulator (LDO5V/LDO15V) 10.5. Switch and Hall Sensor IC Inputs（High Voltage Inputs） 10.6. Oscillator 10.7. Reset Generator and Standby Time 10.8. Data Flash 10.9. Program Flash 10.10. LIN 10.11. 12-V High-Side Driver (HSD_VB) 10.12. 5-V High-Side Driver (HSD_VCC) 10.13. Low-Side Drivers 10.14. 10-Bit AD 10.15. DC characteristics 10.16. SPI 10.17. UART 11. Application Circuit Example 12. Package Information 12.1. Package Dimensions 12.2. Marking 13. IC Usage Considerations 13.1. Notes on Handling of ICs 13.2. Points to Remember on Handling of ICs RESTRICTIONS ON PRODUCT USE
TB9M001FTG
9.2. LINPHY
Single responder-only LIN Phy channel Compliant with the ISO 17987-4, ISO 17987-7 12 V electrical physical layer (EPL), and SAE J2602 standards Withstands an ESD of ±6 kV (IEC 61000-4-2:2008, contact discharge, 150 pF, 330 Ω) Output slope control to reduce conducted EMI noise Programmable slew rate (Low Slope mode<10kbps>, Normal Slope mode<20kbps>, Fast Baud Rate mode<250kbps>) The values enclosed in < > indicate approximate baud rates. The figures enclosed between parentheses above are estimated baud rates. Output driver with a current limiter Thermal shutdown (TSD) circuit in the vicinity of the output driver A circuit that detects a wake-up request pulse from the LIN bus and notifies a system controller, PMU, etc. of the wake-up request Maximum pulse width of a wake-up request: 150 µs as specified by the LIN Specification The system control er, PMU, and other components perform the wake-up process upon receiving this notification, transition from low-power mode to Active mode, and issue an interrupt request to the CPU. W akeUp LPF Wake Up VB APB 30kΩ LPF WakeUp RXD ctrl. LIN Receiver UART Curr.Limit Slope Ctrl. Dominant TXD Timeout TSD Timer LIN ctrl. Transmitter LINGND normal/sleep
9.2.1 LINPHY Block Diagram
© 2 025 8 2025-05-30 Toshiba Electronic Devices & Storage Corporation Rev. 1.0 Document Outline 1. Description 2. Applications 3. Features 4. Functions 5. Block Diagram 6. Pin Assignments 7. Pin Description 8. I/O Equivalent Circuits 9. Functional Description 9.1. CPU 9.1.1. Overview 9.1.2. Arm® Cortex®-M0 Processor 9.1.3. Configurable Options 9.1.4. External Signals 9.1.5. Module Organization 9.2. LINPHY 9.3. LINCNT/UART1 9.4. SPI 9.4.1. External Signals 9.5. GPIO 9.6. 10bit Analog Digital Converter (GADC) 9.7. Low Side Drivers (LSD) 9.8. High Side Drivers (HSD) 9.9. High Voltage Inputs (HVIF) 9.10. Memory Map 10. Electrical Characteristics 10.1. Absolute Maximum Ratings 10.2. Operating Ranges 10.3. Overall Electrical Characteristics 10.4. 5-V/1.5-V Regulator (LDO5V/LDO15V) 10.5. Switch and Hall Sensor IC Inputs（High Voltage Inputs） 10.6. Oscillator 10.7. Reset Generator and Standby Time 10.8. Data Flash 10.9. Program Flash 10.10. LIN 10.11. 12-V High-Side Driver (HSD_VB) 10.12. 5-V High-Side Driver (HSD_VCC) 10.13. Low-Side Drivers 10.14. 10-Bit AD 10.15. DC characteristics 10.16. SPI 10.17. UART 11. Application Circuit Example 12. Package Information 12.1. Package Dimensions 12.2. Marking 13. IC Usage Considerations 13.1. Notes on Handling of ICs 13.2. Points to Remember on Handling of ICs RESTRICTIONS ON PRODUCT USE