User's Manual: Hardware RA2L2 (Renesas) - 4

Preface 1. About this document This manual is generally organized into an overview of the product, descriptions of the CPU, system control functions, peripheral functions, electrical characteristics, and usage notes. This manual describes the product specification of the microcontroller (MCU) superset. Depending on your product, some pins, registers, or functions might not exist. Address space that store unavailable registers are reserved. 2. Audience This manual is written for system designers who are designing and programming applications using the Renesas Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU. 3. Renesas Publications Renesas provides the following documents. Before using any of these documents, visit www.renesas.com for the most up-to-date version of the document.
Component Document Type Description
Microcontrollers Data sheet Features, overview, and electrical characteristics of the MCU User’s Manual: Hardware MCU specifications such as pin assignments, memory maps, peripheral functions, electrical characteristics, timing diagrams, and operation descriptions Application Notes Technical notes, board design guidelines, and software migration information Technical Update (TU) Preliminary reports on product specifications such as restriction and errata Software User’s Manual: Software API reference and programming information Application Notes Project files, guidelines for software programming, and application examples to develop embedded software applications Tools & Kits, Solutions User’s Manual: Development Tools User’s manual and quick start guide for developing embedded software applications with Development Kits (DK), Starter Kits User’s Manual: Software (SK), Promotion Kits (PK), Product Examples (PE), and Application Examples (AE) Quick Start Guide Application Notes Project files, guidelines for software programming, and application examples to develop embedded software applications Document Outline Cover Notice General Precautions Preface Contents Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. CPU 2.1 Overview 2.1.1 CPU 2.1.2 Debug 2.1.3 Operating Frequency 2.1.4 Block Diagram 2.2 Implementation Options 2.3 SWD Interface 2.4 Debug Function 2.4.1 Debug Mode Definition 2.4.2 Debug Mode Effects 2.4.2.1 Low power mode 2.4.2.2 Reset 2.5 Programmers Model 2.5.1 Address Spaces 2.5.2 Cortex-M23 Peripheral Address Map 2.5.3 External Debug Address Map 2.5.4 CoreSight ROM Table 2.5.4.1 ROM entries 2.5.4.2 CoreSight component registers 2.5.5 DBGREG Module 2.5.5.1 DBGSTR : Debug Status Register 2.5.5.2 DBGSTOPCR : Debug Stop Control Register 2.5.5.3 DBGREG CoreSight component registers 2.5.6 OCDREG Module 2.5.6.1 IAUTHn : ID Authentication Code Register (n = 0 to 3) 2.5.6.2 MCUSTAT : MCU Status Register 2.5.6.3 MCUCTRL : MCU Control Register 2.5.6.4 OCDREG CoreSight component registers 2.6 SysTick Timer 2.7 OCD Emulator Connection 2.7.1 Unlock ID Code 2.7.2 DBGEN 2.7.3 Restrictions on Connecting an OCD emulator 2.7.3.1 Starting connection while in low power mode 2.7.3.2 Changing low power mode while in OCD mode 2.7.3.3 Modify the unlock ID code in OSIS 2.7.3.4 Connecting sequence and SWD authentication 2.8 References 2.9 Usage Notes 3. Operating Modes 3.1 Operating Mode Types and Selection 3.2 Details of Operating Modes 3.2.1 Single-Chip Mode 3.2.2 SCI Boot Mode or I2C Boot Mode 3.3 Operating Modes Transitions 3.3.1 Operating Mode Transitions as Determined by the Mode-Setting Pin 4. Address Space 4.1 Address Space 5. Resets 5.1 Overview 5.2 Register Descriptions 5.2.1 RSTSR0 : Reset Status Register 0 5.2.2 RSTSR1 : Reset Status Register 1 5.2.3 RSTSR2 : Reset Status Register 2 5.3 Operation 5.3.1 RES Pin Reset 5.3.2 Power-On Reset 5.3.3 Voltage Monitor Reset 5.3.4 Independent Watchdog Timer Reset 5.3.5 Watchdog Timer Reset 5.3.6 Software Reset 5.3.7 Determination of Cold/Warm Start 5.3.8 Determination of Reset Generation Source 5.4 Usage Notes 5.4.1 Note on RES pin reset 6. Option-Setting Memory 6.1 Overview 6.2 Register Descriptions 6.2.1 OFS0 : Option Function Select Register 0 6.2.2 OFS1 : Option Function Select Register 1 6.2.3 MPU Registers 6.2.4 AWS : Access Window Setting Register 6.2.5 OSIS : OCD/Serial Programmer ID Setting Register 6.3 Setting Option-Setting Memory 6.3.1 Allocation of Data in Option-Setting Memory 6.3.2 Setting Data for Programming Option-Setting Memory 6.4 Usage Notes 6.4.1 Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory 6.4.2 Note on FSPR Bit 7. Low Voltage Detection (LVD) 7.1 Overview 7.2 Register Descriptions 7.2.1 LVCMPCR : Voltage Monitor Circuit Control Register 7.2.2 LVDLVLR : Voltage Detection Level Select Register 7.2.3 LVD1CR0 : Voltage Monitor 1 Circuit Control Register 0 7.2.4 LVD2CR0 : Voltage Monitor 2 Circuit Control Register 0 7.2.5 LVD1CR1 : Voltage Monitor 1 Circuit Control Register 7.2.6 LVD1SR : Voltage Monitor 1 Circuit Status Register 7.2.7 LVD2CR1 : Voltage Monitor 2 Circuit Control Register 1 7.2.8 LVD2SR : Voltage Monitor 2 Circuit Status Register 7.3 VCC Input Voltage Monitor 7.3.1 Monitoring Vdet0 7.3.2 Monitoring Vdet1 7.3.3 Monitoring Vdet2 7.4 Reset from Voltage Monitor 0 7.5 Interrupt and Reset from Voltage Monitor 1 7.6 Interrupt and Reset from Voltage Monitor 2 7.7 Event Link Controller (ELC) Output 7.7.1 Interrupt Handling and Event Linking 8. Clock Generation Circuit 8.1 Overview 8.2 Register Descriptions 8.2.1 SCKDIVCR : System Clock Division Control Register 8.2.2 SCKSCR : System Clock Source Control Register 8.2.3 MEMWAIT : Memory Wait Cycle Control Register for Code Flash 8.2.4 FLDWAITR : Memory Wait Cycle Control Register for Data Flash 8.2.5 MOSCCR : Main Clock Oscillator Control Register 8.2.6 SOSCCR : Sub-Clock Oscillator Control Register 8.2.7 LOCOCR : Low-Speed On-Chip Oscillator Control Register 8.2.8 HOCOCR : High-Speed On-Chip Oscillator Control Register 8.2.9 MOCOCR : Middle-Speed On-Chip Oscillator Control Register 8.2.10 OSCSF : Oscillation Stabilization Flag Register 8.2.11 OSTDCR : Oscillation Stop Detection Control Register 8.2.12 OSTDSR : Oscillation Stop Detection Status Register 8.2.13 MOSCWTCR : Main Clock Oscillator Wait Control Register 8.2.14 HOCOWTCR : High-Speed On-Chip Oscillator Wait Control Register 8.2.15 MOMCR : Main Clock Oscillator Mode Oscillation Control Register 8.2.16 SOMCR : Sub-Clock Oscillator Mode Control Register 8.2.17 SOMRG : Sub-Clock Oscillator Margin Check Register 8.2.18 CKOCR : Clock Out Control Register 8.2.19 LOCOUTCR : LOCO User Trimming Control Register 8.2.20 MOCOUTCR : MOCO User Trimming Control Register 8.2.21 HOCOUTCR : HOCO User Trimming Control Register 8.3 Main Clock Oscillator 8.3.1 Connecting a Crystal Resonator 8.3.2 External Clock Input 8.3.3 Notes on External Clock Input 8.4 Sub-Clock Oscillator 8.4.1 Connecting a 32.768-kHz Crystal Resonator 8.5 Oscillation Stop Detection Function 8.5.1 Oscillation Stop Detection and Operation after Detection 8.5.2 Oscillation Stop Detection Interrupts 8.6 Internal Clock 8.6.1 System Clock (ICLK) 8.6.2 Peripheral Module Clock (PCLKB, PCLKD) 8.6.3 USB Clock (USBCLK) 8.6.4 CAN Clock (CANMCLK) 8.6.5 CAC Clock (CACCLK) 8.6.6 UARTA-dedicated Clock (UARTAMCLK, UARTASCLK, UARTALOCLK, UARTAHOCLK, UARTAMOCLK) 8.6.7 RTC-Dedicated Clock (RTCSCLK, RTCS128CLK, RTCLCLK) 8.6.8 IWDT-Dedicated Clock (IWDTCLK) 8.6.9 AGTW-Dedicated Clock (AGTSCLK, AGTLCLK) 8.6.10 SysTick Timer-Dedicated Clock (SYSTICCLK) 8.6.11 External Pin Output Clock (CLKOUT) 8.7 Usage Notes 8.7.1 Notes on Clock Generation Circuit 8.7.2 Notes on Resonator 8.7.3 Notes on Board Design 8.7.4 Notes on Resonator Connect Pin 9. Clock Frequency Accuracy Measurement Circuit (CAC) 9.1 Overview 9.2 Register Descriptions 9.2.1 CACR0 : CAC Control Register 0 9.2.2 CACR1 : CAC Control Register 1 9.2.3 CACR2 : CAC Control Register 2 9.2.4 CAICR : CAC Interrupt Control Register 9.2.5 CASTR : CAC Status Register 9.2.6 CAULVR : CAC Upper-Limit Value Setting Register 9.2.7 CALLVR : CAC Lower-Limit Value Setting Register 9.2.8 CACNTBR : CAC Counter Buffer Register 9.3 Operation 9.3.1 Measuring Clock Frequency 9.3.2 Digital Filtering of Signals on CACREF Pin 9.4 Interrupt Requests 9.5 Usage Notes 9.5.1 Settings for the Module-Stop Function 10. Low Power Modes 10.1 Overview 10.2 Register Descriptions 10.2.1 SBYCR : Standby Control Register 10.2.2 MSTPCRA : Module Stop Control Register A 10.2.3 MSTPCRB : Module Stop Control Register B 10.2.4 MSTPCRC : Module Stop Control Register C 10.2.5 MSTPCRD : Module Stop Control Register D 10.2.6 OPCCR : Operating Power Control Register 10.2.7 SOPCCR : Sub Operating Power Control Register 10.2.8 SNZCR : Snooze Control Register 10.2.9 SNZEDCR0 : Snooze End Control Register 0 10.2.10 SNZREQCR0 : Snooze Request Control Register 0 10.2.11 PSMCR : Power Save Memory Control Register 10.2.12 SYOCDCR : System Control OCD Control Register 10.2.13 LSMRWDIS : Low Speed Module R/W Disable Control Register 10.2.14 LPOPT : Lower Power Operation Control Register 10.3 Reducing Power Consumption by Switching Clock Signals 10.4 Module-Stop Function 10.5 Function for Lower Operating Power Consumption 10.5.1 Setting Operating Power Control Mode 10.5.2 Operating Range 10.6 Sleep Mode 10.6.1 Transitioning to Sleep Mode 10.6.2 Canceling Sleep Mode 10.7 Software Standby Mode 10.7.1 Transition to Software Standby Mode 10.7.2 Canceling Software Standby Mode 10.7.3 Example of Software Standby Mode Application 10.8 Snooze Mode 10.8.1 Transition to Snooze Mode 10.8.2 Canceling Snooze Mode 10.8.3 Returning from Snooze Mode to Software Standby Mode 10.8.4 Snooze Operation Example 10.9 Usage Notes 10.9.1 Register Access 10.9.2 I/O Port pin states 10.9.3 Module-Stop State of DTC 10.9.4 Internal Interrupt Sources 10.9.5 Transitioning to Low Power Modes 10.9.6 Timing of WFI Instruction 10.9.7 Writing to the WDT/IWDT Registers by DTC in Sleep Mode or Snooze Mode 10.9.8 Oscillators in Snooze Mode 10.9.9 Snooze Mode Entry by RXD0 Falling Edge 10.9.10 Using UART of SCI0 in Snooze Mode 10.9.11 Conditions of A/D Conversion Start in Snooze Mode 10.9.12 ELC Events in Snooze Mode 10.9.13 Module-Stop Function for ADC120 10.9.14 Module-Stop Function for an Unused Circuit 11. Register Write Protection 11.1 Overview 11.2 Register Descriptions 11.2.1 PRCR : Protect Register 12. Interrupt Controller Unit (ICU) 12.1 Overview 12.2 Register Descriptions 12.2.1 IRQCRi : IRQ Control Register i (i = 0 to 7) 12.2.2 NMISR : Non-Maskable Interrupt Status Register 12.2.3 NMIER : Non-Maskable Interrupt Enable Register 12.2.4 NMICLR : Non-Maskable Interrupt Status Clear Register 12.2.5 NMICR : NMI Pin Interrupt Control Register 12.2.6 IELSRn : ICU Event Link Setting Register n (n = 0 to 31) 12.2.7 SELSR0 : SYS Event Link Setting Register 12.2.8 WUPEN : Wake Up Interrupt Enable Register 12.2.9 WUPEN2 : Wake Up Interrupt Enable Register 2 12.2.10 IELEN : ICU Event Enable Register 12.3 Vector Table 12.3.1 Interrupt Vector Table 12.3.2 Event Number 12.3.3 ICU and DTC Event Number 12.4 Interrupt Operation 12.4.1 Detecting Interrupts 12.5 Interrupt setting procedure 12.5.1 Enabling Interrupt Requests 12.5.2 Disabling Interrupt Requests 12.5.3 Polling for interrupts 12.5.4 Selecting Interrupt Request Destinations 12.5.4.1 CPU interrupt request 12.5.4.2 DTC activation 12.5.5 Digital Filter 12.5.6 External Pin Interrupts 12.6 Non-Maskable Interrupt Operation 12.7 Return from Low Power Modes 12.7.1 Return from Sleep Mode 12.7.2 Return from Software Standby Mode 12.7.3 Return from Snooze Mode 12.8 Using the WFI Instruction with Non-Maskable Interrupts 12.9 Reference 13. Buses 13.1 Overview 13.2 Description of Buses 13.2.1 Main Buses 13.2.2 Slave Interface 13.2.3 Parallel Operations 13.2.4 Restriction on Endianness 13.2.5 Restriction on Exclusive Access 13.3 Register Descriptions 13.3.1 BUSMCNTx : Master Bus Control Register x (x = SYS, DMA) 13.3.2 BUSnERRADD : Bus Error Address Register n (n = 3, 4) 13.3.3 BUSnERRSTAT : BUS Error Status Register n (n = 3, 4) 13.4 Bus Error Monitoring Section 13.4.1 Error Type that Occurs by Bus 13.4.2 Operation when a Bus Error Occurs 13.4.3 Conditions for issuing illegal Address Access Errors 13.5 References 14. Memory Protection Unit (MPU) 14.1 Overview 14.2 CPU Stack Pointer Monitor 14.2.1 Protecting the Registers 14.2.2 Overflow and Underflow Errors 14.2.3 Register Descriptions 14.2.3.1 MSPMPUSA : Main Stack Pointer (MSP) Monitor Start Address Register 14.2.3.2 MSPMPUEA : Main Stack Pointer (MSP) Monitor End Address Register 14.2.3.3 PSPMPUSA : Process Stack Pointer (PSP) Monitor Start Address Register 14.2.3.4 PSPMPUEA : Process Stack Pointer (PSP) Monitor End Address Register 14.2.3.5 MSPMPUOAD, PSPMPUOAD : Stack Pointer Monitor Operation After Detection Register 14.2.3.6 MSPMPUCTL, PSPMPUCTL : Stack Pointer Monitor Access Control Register 14.2.3.7 MSPMPUPT, PSPMPUPT : Stack Pointer Monitor Protection Register 14.3 Arm MPU 14.4 Bus Master MPU 14.4.1 Register Descriptions 14.4.1.1 MMPUSAn : Group A Region n Start Address Register (n = 0 to 3) 14.4.1.2 MMPUEAn : Group A Region n End Address Register (n = 0 to 3) 14.4.1.3 MMPUACAn : Group A Region n access control register (n = 0 to 3) 14.4.1.4 MMPUCTLA : Bus Master MPU Control Register 14.4.1.5 MMPUPTA : Group A Protection of Register 14.4.2 Operation 14.4.2.1 Memory protection 14.4.2.2 Protecting the registers 14.4.2.3 Memory protection error 14.5 Bus Slave MPU 14.5.1 Register Descriptions 14.5.1.1 SMPUMBIU : Access Control Register for Memory Bus 1 14.5.1.2 SMPUSRAM0 : Access Control Register for Memory Bus 4 14.5.1.3 SMPUP0BIU : Access Control Register for Internal Peripheral Bus 1 14.5.1.4 SMPUP2BIU : Access Control Register for Internal Peripheral Bus 3 14.5.1.5 SMPUP6BIU : Access Control Register for Internal Peripheral Bus 7 14.5.1.6 SMPUFBIU : Access Control Register for Internal Peripheral Bus 9 14.5.1.7 SMPUCTL : Slave MPU Control Register 14.5.2 Functions 14.5.2.1 Memory protection 14.5.2.2 Protecting the registers 14.5.2.3 Memory protection error 14.6 Security MPU 14.6.1 Register Descriptions (Option-Setting Memory) 14.6.1.1 SECMPUPCSn : Security MPU Program Counter Start Address Register n (n = 0, 1) 14.6.1.2 SECMPUPCEn : Security MPU Program Counter End Address Register n (n = 0, 1) 14.6.1.3 SECMPUS0 : Security MPU Region 0 Start Address Register 14.6.1.4 SECMPUE0 : Security MPU Region 0 End Address Register 14.6.1.5 SECMPUS1 : Security MPU Region 1 Start Address Register 14.6.1.6 SECMPUE1 : Security MPU Region 1 End Address Register 14.6.1.7 SECMPUS2 : Security MPU Region 2 Start Address Register 14.6.1.8 SECMPUE2 : Security MPU Region 2 End Address Register 14.6.1.9 SECMPUS3 : Security MPU Region 3 Start Address Register 14.6.1.10 SECMPUE3 : Security MPU Region 3 End Address Register 14.6.1.11 SECMPUAC : Security MPU Access Control Register 14.6.2 Memory Protection 14.7 Usage Notes 14.7.1 Notes on the Use of a Debugger 14.8 References 15. Data Transfer Controller (DTC) 15.1 Overview 15.2 Register Descriptions 15.2.1 MRA : DTC Mode Register A 15.2.2 MRB : DTC Mode Register B 15.2.3 SAR : DTC Transfer Source Register 15.2.4 DAR : DTC Transfer Destination Register 15.2.5 CRA : DTC Transfer Count Register A 15.2.6 CRB : DTC Transfer Count Register B 15.2.7 DTCCR : DTC Control Register 15.2.8 DTCVBR : DTC Vector Base Register 15.2.9 DTCST : DTC Module Start Register 15.2.10 DTCSTS : DTC Status Register 15.3 Activation Sources 15.3.1 Allocating Transfer Information and DTC Vector Table 15.4 Operation 15.4.1 Transfer Information Read Skip Function 15.4.2 Transfer Information Write-Back Skip Function 15.4.3 Normal Transfer Mode 15.4.4 Repeat Transfer Mode 15.4.5 Block Transfer Mode 15.4.6 Chain Transfer 15.4.7 Operation Timing 15.4.8 Execution Cycles of DTC 15.4.9 DTC Bus Mastership Release Timing 15.5 DTC Setting Procedure 15.6 Examples of DTC Usage 15.6.1 Normal Transfer 15.6.2 Chain transfer 15.6.3 Chain Transfer when Counter = 0 15.7 Interrupt 15.7.1 Interrupt Sources 15.8 Event Link 15.9 Low Power Consumption Function 15.10 Usage Notes 15.10.1 Transfer Information Start Address 16. Event Link Controller (ELC) 16.1 Overview 16.2 Register Descriptions 16.2.1 ELCR : Event Link Controller Register 16.2.2 ELSEGRn : Event Link Software Event Generation Register n (n = 0, 1) 16.2.3 ELSRn : Event Link Setting Register n (n = 0 to 3, 8, 9, 14, 15) 16.3 Operation 16.3.1 Relation between Interrupt Handling and Event Linking 16.3.2 Linking Events 16.3.3 Example of Procedure for Linking Events 16.4 Usage Notes 16.4.1 Linking DTC Transfer End Signals as Events 16.4.2 Setting Clocks 16.4.3 Module-Stop Function Setting 16.4.4 ELC Delay Time 17. I/O Ports 17.1 Overview 17.2 Register Descriptions 17.2.1 PCNTR1/PODR/PDR : Port Control Register 1 17.2.2 PCNTR2/EIDR/PIDR : Port Control Register 2 17.2.3 PCNTR3/PORR/POSR : Port Control Register 3 17.2.4 PCNTR4/EORR/EOSR : Port Control Register 4 17.2.5 PmnPFS/PmnPFS_HA/PmnPFS_BY : Port mn Pin Function Select Register (m = 0 to 5, 9, n = 00 to 15) 17.2.6 P20nPFS/P20nPFS_HA/P20nPFS_BY : Port 20n Pin Function Select Register (n = 0) 17.2.7 P2nPFS/P2nPFS_HA/P2nPFS_BY : Port 2n Pin Function Select Register (n = 12, 13) 17.2.8 P40nPFS/P40nPFS_HA/P40nPFS_BY : Port 40n Pin Function Select Register (n = 7 to 9) 17.2.9 PWPR : Write-Protect Register 17.2.10 PRWCNTR : Port Read Wait Control Register 17.3 Operation 17.3.1 General I/O Ports 17.3.2 Port Function Select 17.3.3 Port Group Function for ELC 17.3.3.1 Behavior When ELC_PORT1 or 2 is Input from ELC 17.3.3.2 Behavior When an Event Pulse is Output to ELC 17.3.4 Wait Function for Port Read 17.4 Handling of Unused Pins 17.5 Usage Notes 17.5.1 Procedure for Specifying the Pin Functions 17.5.2 Procedure for Using Port Group Input 17.5.3 Port Output Data Register (PODR) Summary 17.5.4 Notes on Using Analog Functions 17.6 Peripheral Select Settings for Each Product 18. Key Interrupt Function (KINT) 18.1 Overview 18.2 Register Descriptions 18.2.1 KRCTL : Key Return Control Register 18.2.2 KRF : Key Return Flag Register 18.2.3 KRM : Key Return Mode Register 18.3 Operation 18.3.1 Operation When Not Using the Key Interrupt Flags (KRCTL.KRMD = 0) 18.3.2 Operation When Using the Key Interrupt Flags (KRCTL.KRMD = 1) 18.4 Usage Notes 19. Port Output Enable for GPT (POEG) 19.1 Overview 19.2 Register Descriptions 19.2.1 POEGGn : POEG Group n Setting Register (n = A, B) 19.3 Output-Disable Control Operation 19.3.1 Pin Input Level Detection Operation 19.3.1.1 Digital Filter 19.3.2 Output-Disable Requests from the GPT 19.3.3 Output-Disable Control Using Detection of Stopped Oscillation 19.3.4 Output-Disable Control Using Registers 19.3.5 Release from Output-Disable 19.4 Interrupt Sources 19.5 External Trigger Output to the GPT 19.6 Usage Notes 19.6.1 Transition to Software Standby Mode 19.6.2 Specifying Pins Associated with the GPT 20. General PWM Timer (GPT) 20.1 Overview 20.2 Register Descriptions 20.2.1 GTWP : General PWM Timer Write-Protection Register 20.2.2 GTSTR : General PWM Timer Software Start Register 20.2.3 GTSTP : General PWM Timer Software Stop Register 20.2.4 GTCLR : General PWM Timer Software Clear Register 20.2.5 GTSSR : General PWM Timer Start Source Select Register 20.2.6 GTPSR : General PWM Timer Stop Source Select Register 20.2.7 GTCSR : General PWM Timer Clear Source Select Register 20.2.8 GTUPSR : General PWM Timer Up Count Source Select Register 20.2.9 GTDNSR : General PWM Timer Down Count Source Select Register 20.2.10 GTICASR : General PWM Timer Input Capture Source Select Register A 20.2.11 GTICBSR : General PWM Timer Input Capture Source Select Register B 20.2.12 GTCR : General PWM Timer Control Register 20.2.13 GTUDDTYC : General PWM Timer Count Direction and Duty Setting Register 20.2.14 GTIOR : General PWM Timer I/O Control Register 20.2.15 GTINTAD : General PWM Timer Interrupt Output Setting Register 20.2.16 GTST : General PWM Timer Status Register 20.2.17 GTBER : General PWM Timer Buffer Enable Register 20.2.18 GTCNT : General PWM Timer Counter 20.2.19 GTCCRk : General PWM Timer Compare Capture Register k (k = A to F) 20.2.20 GTPR : General PWM Timer Cycle Setting Register 20.2.21 GTPBR : General PWM Timer Cycle Setting Buffer Register 20.2.22 GTDTCR : General PWM Timer Dead Time Control Register 20.2.23 GTDVU : General PWM Timer Dead Time Value Register U 20.2.24 OPSCR : Output Phase Switching Control Register 20.3 Operation 20.3.1 Basic Operation 20.3.1.1 Counter operation 20.3.1.2 Waveform output by compare match 20.3.1.3 Input Capture Function 20.3.2 Buffer Operation 20.3.2.1 GTPR Register Buffer Operation 20.3.2.2 Buffer Operation for GTCCRA and GTCCRB Registers 20.3.3 PWM Output Operating Mode 20.3.3.1 Saw-Wave PWM Mode 20.3.3.2 Saw-Wave One-Shot Pulse Mode 20.3.3.3 Triangle-Wave PWM Mode 1 (32-Bit Transfer at Trough) 20.3.3.4 Triangle-Wave PWM Mode 2 (32-Bit Transfer at Crest and Trough) 20.3.3.5 Triangle-Wave PWM Mode 3 (64-Bit Transfer at Trough) 20.3.4 Automatic Dead Time Setting Function 20.3.5 Count Direction Changing Function 20.3.6 Function of Output Duty 0% and 100% 20.3.7 Hardware Count Start/Count Stop and Clear Operation 20.3.7.1 Hardware Start Operation 20.3.7.2 Hardware Stop Operation 20.3.7.3 Hardware Clear Operation 20.3.8 Synchronized Operation 20.3.8.1 Synchronized Operation by Software 20.3.8.2 Synchronized Operation by Hardware 20.3.9 PWM Output Operation Examples 20.3.10 Phase Counting Function 20.3.11 Output Phase Switching (GPT_OPS) 20.3.11.1 Input Selection and Synchronization of External Input Signal 20.3.11.2 Input Sampling 20.3.11.3 Input Phase Decode 20.3.11.4 Rotation Direction Control 20.3.11.5 Output Selection Control 20.3.11.6 Output Selection Control (Group Output Disable Function) 20.3.11.7 Event Link Controller (ELC) Output 20.3.11.8 GPT_OPS Start Operation Setting Flow 20.4 Interrupt Sources 20.4.1 Interrupt Sources 20.4.2 DTC Activation 20.5 Operations Linked by ELC 20.5.1 Event Signal Output to ELC 20.5.2 Event Signal Inputs from ELC 20.6 Noise Filter Function 20.7 Protection Function 20.7.1 Write-Protection for Registers 20.7.2 Disabling of Buffer Operation 20.7.3 GTIOCnm Pin Output Negate Control (n = 0, 4 to 9, m = A, B) 20.8 Initialization Method of Output Pins 20.8.1 Pin Settings after Reset 20.8.2 Pin Initialization Due to Error during Operation 20.9 Usage Notes 20.9.1 Module-Stop Function Setting 20.9.2 GTCCRn Settings during Compare Match Operation (n = A to F) 20.9.3 Setting Range for GTCNT Counter 20.9.4 Starting and Stopping the GTCNT Counter 20.9.5 Priority Order of Each Event 21. Low Power Asynchronous General Purpose Timer (AGTW) 21.1 Overview 21.2 Register Descriptions 21.2.1 AGT : AGT Counter Register 21.2.2 AGTCMA : AGT Compare Match A Register 21.2.3 AGTCMB : AGT Compare Match B Register 21.2.4 AGTCR : AGT Control Register 21.2.5 AGTMR1 : AGT Mode Register 1 21.2.6 AGTMR2 : AGT Mode Register 2 21.2.7 AGTIOC : AGT I/O Control Register 21.2.8 AGTISR : AGT Event Pin Select Register 21.2.9 AGTCMSR : AGT Compare Match Function Select Register 21.2.10 AGTIOSEL : AGT Pin Select Register 21.3 Operation 21.3.1 Reload Register and Counter Rewrite Operation 21.3.2 Reload Register and AGT Compare Match A/B Register Rewrite Operation 21.3.3 Timer Mode 21.3.4 Pulse Output Mode 21.3.5 Event Counter Mode 21.3.6 Pulse Width Measurement Mode 21.3.7 Pulse Period Measurement Mode 21.3.8 Compare Match Function 21.3.9 Output Settings for Each Mode 21.3.10 Standby Mode 21.3.11 Interrupt Sources 21.3.12 Event Signal Output to ELC 21.4 Usage Notes 21.4.1 Count Operation Start and Stop Control 21.4.2 Access to Counter Register 21.4.3 When Changing Mode 21.4.4 Output Pin Setting 21.4.5 Digital Filter 21.4.6 How to Calculate Event Number, Pulse Width, and Pulse Period 21.4.7 When Count is Forcibly Stopped by TSTOP Bit 21.4.8 When Selecting AGTW0 Underflow as the Count Source 21.4.9 Module-stop Function 22. Realtime Clock (RTC) 22.1 Overview 22.2 Register Descriptions 22.2.1 R64CNT : 64-Hz Counter 22.2.2 RSECCNT : Second Counter (in Calendar Count Mode) 22.2.3 RMINCNT : Minute Counter (in Calendar Count Mode) 22.2.4 RHRCNT : Hour Counter (in Calendar Count Mode) 22.2.5 RWKCNT : Day-of-Week Counter (in Calendar Count Mode) 22.2.6 BCNTn : Binary Counter n (n = 0 to 3) (in Binary Count Mode) 22.2.7 RDAYCNT : Day Counter 22.2.8 RMONCNT : Month Counter 22.2.9 RYRCNT : Year Counter 22.2.10 RSECAR : Second Alarm Register (in Calendar Count Mode) 22.2.11 RMINAR : Minute Alarm Register (in Calendar Count Mode) 22.2.12 RHRAR : Hour Alarm Register (in Calendar Count Mode) 22.2.13 RWKAR : Day-of-Week Alarm Register (in Calendar Count Mode) 22.2.14 BCNTnAR : Binary Counter n Alarm Register (n = 0 to 3) (in Binary Count Mode) 22.2.15 RDAYAR : Date Alarm Register (in Calendar Count Mode) 22.2.16 RMONAR : Month Alarm Register (in Calendar Count Mode) 22.2.17 RYRAR : Year Alarm Register (in Calendar Count Mode) 22.2.18 RYRAREN : Year Alarm Enable Register (in Calendar Count Mode) 22.2.19 BCNTnAER : Binary Counter n Alarm Enable Register (n = 0, 1) (in Binary Count Mode) 22.2.20 BCNT2AER : Binary Counter 2 Alarm Enable Register (in Binary Count Mode) 22.2.21 BCNT3AER : Binary Counter 3 Alarm Enable Register (in Binary Count Mode) 22.2.22 RCR1 : RTC Control Register 1 22.2.23 RCR2 : RTC Control Register 2 (in Calendar Count Mode) 22.2.24 RCR2 : RTC Control Register 2 (in Binary Count Mode) 22.2.25 RCR4 : RTC Control Register 4 22.2.26 RFRL : Frequency Register L 22.2.27 RFRH : Frequency Register H 22.2.28 RADJ : Time Error Adjustment Register 22.3 Operation 22.3.1 Outline of Initial Settings of Registers after Power On 22.3.2 Operation mode, Clock and Count Mode Setting Procedure 22.3.3 Setting the Time 22.3.4 30-Second Adjustment 22.3.5 Reading 64-Hz Counter and Time 22.3.6 Alarm Function 22.3.7 Procedure for Disabling Alarm Interrupt 22.3.8 Time Error Adjustment Function 22.3.8.1 Automatic adjustment 22.3.8.2 Adjustment by software 22.3.8.3 Procedure to change the mode of adjustment 22.3.8.4 Procedure to stop adjustment 22.4 Interrupt Sources 22.5 Event Link Output 22.5.1 Interrupt Handling and Event Linking 22.6 Usage Notes 22.6.1 Register Writing during Counting 22.6.2 Use of Periodic Interrupts 22.6.3 RTCOUT (1-Hz/64-Hz) Clock Output 22.6.4 Transitions to Low Power Modes after Setting Registers 22.6.5 Notes on Writing to and Reading from Registers 22.6.6 Changing the Count Mode 22.6.7 Initialization Procedure When the RTC Is Not to Be Used 23. Watchdog Timer (WDT) 23.1 Overview 23.2 Register Descriptions 23.2.1 WDTRR : WDT Refresh Register 23.2.2 WDTCR : WDT Control Register 23.2.3 WDTSR : WDT Status Register 23.2.4 WDTRCR : WDT Reset Control Register 23.2.5 WDTCSTPR : WDT Count Stop Control Register 23.2.6 Option Function Select Register 0 (OFS0) 23.3 Operation 23.3.1 Count Operation in each Start Mode 23.3.1.1 Register start mode 23.3.1.2 Auto start mode 23.3.2 Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers 23.3.3 Refresh Operation 23.3.4 Status Flags 23.3.5 Reset Output 23.3.6 Interrupt Sources 23.3.7 Reading the Down-Counter Value 23.3.8 Association between Option Function Select Register 0 (OFS0) and WDT Registers 23.4 Output to the Event Link Controller (ELC) 23.5 Usage Notes 23.5.1 ICU Event Link Setting Register n (IELSRn) Setting 24. Independent Watchdog Timer (IWDT) 24.1 Overview 24.2 Register Descriptions 24.2.1 IWDTRR : IWDT Refresh Register 24.2.2 IWDTSR : IWDT Status Register 24.2.3 OFS0 : Option Function Select Register 0 24.3 Operation 24.3.1 Auto Start Mode 24.3.2 Refresh Operation 24.3.3 Status Flags 24.3.4 Reset Output 24.3.5 Interrupt Sources 24.3.6 Reading the Down-Counter Value 24.4 Output to the Event Link Controller (ELC) 24.5 Usage Notes 24.5.1 Refresh Operations 24.5.2 Clock Division Ratio Setting 24.5.3 Constraints on the ICU Event Link Setting Register n (IELSRn) Setting 25. USB 2.0 Full-Speed Module (USBFS) 25.1 Overview 25.2 Register Descriptions 25.2.1 SYSCFG : System Configuration Control Register 25.2.2 SYSSTS0 : System Configuration Status Register 0 25.2.3 DVSTCTR0 : Device State Control Register 0 25.2.4 CFIFO/CFIFOL : CFIFO Port Register 25.2.5 DnFIFO/DnFIFOL : DnFIFO Port Register (n = 0, 1) 25.2.6 CFIFOSEL : CFIFO Port Select Register 25.2.7 DnFIFOSEL : DnFIFO Port Select Register (n = 0, 1) 25.2.8 CFIFOCTR : CFIFO Port Control Register 25.2.9 DnFIFOCTR : DnFIFO Port Control Register (n = 0, 1) 25.2.10 INTENB0 : Interrupt Enable Register 0 25.2.11 BRDYENB : BRDY Interrupt Enable Register 25.2.12 NRDYENB : NRDY Interrupt Enable Register 25.2.13 BEMPENB : BEMP Interrupt Enable Register 25.2.14 SOFCFG : SOF Output Configuration Register 25.2.15 INTSTS0 : Interrupt Status Register 0 25.2.16 BRDYSTS : BRDY Interrupt Status Register 25.2.17 NRDYSTS : NRDY Interrupt Status Register 25.2.18 BEMPSTS : BEMP Interrupt Status Register 25.2.19 FRMNUM : Frame Number Register 25.2.20 USBADDR : USB Address Register 25.2.21 USBREQ : USB Request Type Register 25.2.22 USBVAL : USB Request Value Register 25.2.23 USBINDX : USB Request Index Register 25.2.24 USBLENG : USB Request Length Register 25.2.25 DCPCFG : DCP Configuration Register 25.2.26 DCPMAXP : DCP Maximum Packet Size Register 25.2.27 DCPCTR : DCP Control Register 25.2.28 PIPESEL : Pipe Window Select Register 25.2.29 PIPECFG : Pipe Configuration Register 25.2.30 PIPEMAXP : Pipe Maximum Packet Size Register 25.2.31 PIPEPERI : Pipe Cycle Control Register 25.2.32 PIPEnCTR : PIPEn Control Registers (n = 1 to 5) 25.2.33 PIPEnCTR : PIPEn Control Registers (n = 6 to 9) 25.2.34 PIPEnTRE : PIPEn Transaction Counter Enable Register (n = 1 to 5) 25.2.35 PIPEnTRN : PIPEn Transaction Counter Register (n = 1 to 5) 25.3 Operation 25.3.1 System Control 25.3.1.1 Setting data to the USBFS registers 25.3.1.2 Controlling the USB data bus using resistors 25.3.1.3 Example external connection circuits 25.3.2 Interrupts 25.3.3 Interrupt Descriptions 25.3.3.1 BRDY interrupt 25.3.3.2 NRDY interrupt 25.3.3.3 BEMP interrupt 25.3.3.4 Device state transition interrupt (device controller mode) 25.3.3.5 Control transfer stage transition interrupt (device controller mode) 25.3.3.6 Frame update interrupt 25.3.3.7 VBUS interrupt 25.3.3.8 Resume interrupt 25.3.4 Pipe Control 25.3.4.1 Pipe control register switching procedures 25.3.4.2 Transfer types 25.3.4.3 Endpoint number 25.3.4.4 Maximum packet size setting 25.3.4.5 Transaction counter for pipes 1 to 5 in the receiving direction 25.3.4.6 Response PID 25.3.4.7 Data PID sequence bit 25.3.4.8 Response PID = NAK function 25.3.4.9 Auto response mode 25.3.4.10 OUT-NAK mode 25.3.4.11 Null auto response mode 25.3.5 FIFO Buffer 25.3.6 FIFO Buffer Clearing 25.3.7 FIFO Port Functions 25.3.8 DTC Transfers (D0FIFO and D1FIFO Ports) 25.3.9 Control Transfers Using the DCP 25.3.9.1 Control transfers in device controller mode 25.3.10 Bulk Transfers (Pipes 1 to 5) 25.3.11 Interrupt Transfers (Pipes 6 to 9) 25.3.12 Isochronous Transfers (Pipes 1 and 2) 25.3.12.1 Error detection in isochronous transfers 25.3.12.2 DATA-PID 25.3.12.3 Interval counter 25.3.13 SOF Interpolation Function 25.3.14 Pipe Schedule 25.3.14.1 Transfer schedule 25.4 Usage Notes 25.4.1 Settings for the Module-Stop State 25.4.2 Clearing the Interrupt Status Register on Canceling Software Standby Mode 25.4.3 Clearing the Interrupt Status Register after Setting Up the Port Function 25.4.4 Settings for HOCO User Trimming Control Code 26. USB Type-C Interface 26.1 Overview 26.2 Register Descriptions 26.2.1 TCC : TYPE-C Control Register 26.2.2 MEC : Mode Setting and State Control Register 26.2.3 CCC : CC-PHY Control Register 26.2.4 IES : Interrupt Enable Control and Status Register 26.2.5 TCS : Type-CC Connection State and Status Register 26.2.6 TSET : Type-C Related Timer Value Setting Register 26.3 Operation 26.3.1 HW Controlling Mode 26.3.2 CC Timing Control (Debouncing) 26.3.3 Initial Setting 26.3.4 Operation Flow 26.3.4.1 HW Controlling Mode Flow 26.3.5 Interrupt 26.3.6 Usage Notes 26.3.6.1 Module-Stop Function Setting 26.3.6.2 Clock Setting 27. Serial Communications Interface (SCI) 27.1 Overview 27.2 Register Descriptions 27.2.1 RSR : Receive Shift Register 27.2.2 RDR : Receive Data Register 27.2.3 RDRHL : Receive Data Register 27.2.4 FRDRHL/FRDRH/FRDRL : Receive FIFO Data Register 27.2.5 TDR : Transmit Data Register 27.2.6 TDRHL : Transmit Data Register 27.2.7 FTDRHL/FTDRH/FTDRL : Transmit FIFO Data Register 27.2.8 TSR : Transmit Shift Register 27.2.9 SMR : Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 27.2.10 SMR_SMCI : Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) 27.2.11 SCR : Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 27.2.12 SCR_SMCI : Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) 27.2.13 SSR : Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) 27.2.14 SSR_FIFO : Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1) 27.2.15 SSR_SMCI : Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1) 27.2.16 SCMR : Smart Card Mode Register 27.2.17 BRR : Bit Rate Register 27.2.18 MDDR : Modulation Duty Register 27.2.19 SEMR : Serial Extended Mode Register 27.2.20 SNFR : Noise Filter Setting Register 27.2.21 SIMR1 : IIC Mode Register 1 27.2.22 SIMR2 : IIC Mode Register 2 27.2.23 SIMR3 : IIC Mode Register 3 27.2.24 SISR : IIC Status Register 27.2.25 SPMR : SPI Mode Register 27.2.26 FCR : FIFO Control Register 27.2.27 FDR : FIFO Data Count Register 27.2.28 LSR : Line Status Register 27.2.29 CDR : Compare Match Data Register 27.2.30 DCCR : Data Compare Match Control Register 27.2.31 SPTR : Serial Port Register 27.3 Operation in Asynchronous Mode 27.3.1 Serial Data Transfer Format 27.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 27.3.3 Clock 27.3.4 Double-Speed Operation and Frequency of 6 Times the Bit Rate 27.3.5 CTS and RTS Functions 27.3.6 Address Match (Receive Data Match Detection) Function 27.3.7 SCI Initialization in Asynchronous Mode 27.3.8 Serial Data Transmission in Asynchronous Mode 27.3.9 Serial Data Reception in Asynchronous Mode 27.4 Multi-Processor Communication Function 27.4.1 Multi-Processor Serial Data Transmission 27.4.2 Multi-Processor Serial Data Reception 27.5 Operation in Clock Synchronous Mode 27.5.1 Clock 27.5.2 CTS and RTS Functions 27.5.3 SCI Initialization in Clock Synchronous Mode 27.5.4 Serial Data Transmission in Clock Synchronous Mode 27.5.5 Serial Data Reception in Clock Synchronous Mode 27.5.6 Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode 27.6 Operation in Smart Card Interface Mode 27.6.1 Example Connection 27.6.2 Data Format (Except in Block Transfer Mode) 27.6.3 Block Transfer Mode 27.6.4 Receive Data Sampling Timing and Reception Margin 27.6.5 SCI Initialization (Smart Card Interface Mode) 27.6.6 Serial Data Transmission (Except in Block Transfer Mode) 27.6.7 Serial Data Reception (Except in Block Transfer Mode) 27.6.8 Clock Output Control 27.7 Operation in Simple IIC Mode 27.7.1 Generation of Start, Restart, and Stop Conditions 27.7.2 Clock Synchronization 27.7.3 SDAn Output Delay 27.7.4 SCI Initialization in Simple IIC Mode 27.7.5 Operation in Master Transmission in Simple IIC Mode 27.7.6 Master Reception in Simple IIC Mode 27.8 Operation in Simple SPI Mode 27.8.1 States of Pins in Master and Slave Modes 27.8.2 SS Function in Master Mode 27.8.3 SS Function in Slave Mode 27.8.4 Relationship between Clock and Transmit/Receive Data 27.8.5 SCI Initialization in Simple SPI Mode 27.8.6 Transmission and Reception of Serial Data in Simple SPI Mode 27.9 Bit Rate Modulation Function 27.10 Interrupt Sources 27.10.1 Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (Non-FIFO Selected) 27.10.2 Buffer Operation for SCIn_TXI and SCIn_RXI Interrupts (FIFO Selected) 27.10.3 Interrupts in Asynchronous, Clock Synchronous, and Simple SPI Modes 27.10.4 Interrupts in Smart Card Interface Mode 27.10.5 Interrupts in Simple IIC Mode 27.11 Event Linking 27.12 Address Non-match Event Output (SCI0_DCUF) 27.13 Noise Cancellation Function 27.14 Usage Notes 27.14.1 Settings for the Module-Stop Function 27.14.2 SCI Operation during Low Power State 27.14.3 Break Detection and Processing 27.14.4 Mark State and Production of Breaks 27.14.5 Receive Error Flags and Transmit Operation in Clock Synchronous Mode and Simple SPI Mode 27.14.6 Restrictions on Clock Synchronous Transmission in Clock Synchronous Mode and Simple SPI Mode 27.14.7 Restrictions on Using DTC 27.14.8 Notes on Starting Transfer 27.14.9 External Clock Input in Clock Synchronous Mode and Simple SPI Mode 27.14.10 Limitations on Simple SPI Mode 27.14.11 Notes on Transmit Enable Bit (SCR.TE) 27.14.12 Note on Stopping Reception When Using the RTS Function in Asynchronous Mode 28. I3C Bus Interface (I3C) 28.1 Overview 28.1.1 Functional Overview 28.1.2 Block Diagram [I2C/I3C common] 28.2 Registers 28.2.1 List of Registers 28.2.2 PRTS : Protocol Selection Register 28.2.3 BCTL : Bus Control Register 28.2.4 MSDVAD : Master Device Address Register 28.2.5 RSTCTL : Reset Control Register 28.2.6 PRSST : Present State Register 28.2.7 INST : Internal Status Register 28.2.8 INSTE : Internal Status Enable Register 28.2.9 INIE : Internal Interrupt Enable Register 28.2.10 INSTFC : Internal Status Force Register 28.2.11 DVCT : Device Characteristic Table Register 28.2.12 IBINCTL : IBI Notify Control Register 28.2.13 BFCTL : Bus Function Control Register 28.2.14 SVCTL : Slave Control Register 28.2.15 REFCKCTL : Reference Clock Control Register 28.2.16 STDBR : Standard Bit Rate Register 28.2.17 EXTBR : Extended Bit Rate Register 28.2.18 BFRECDT : Bus Free Condition Detection Time Register 28.2.19 BAVLCDT : Bus Available Condition Detection Time Register 28.2.20 BIDLCDT : Bus Idle Condition Detection Time Register 28.2.21 OUTCTL : Output Control Register 28.2.22 INCTL : Input Control Register 28.2.23 TMOCTL : Timeout Control Register 28.2.24 ACKCTL : Acknowledge Control Register 28.2.25 SCSTRCTL : SCL Stretch Control Register 28.2.26 SCSTLCTL : SCL Stalling Control Register 28.2.27 SVTDLG0 : Slave Transfer Data Length Register 0 28.2.28 CNDCTL : Condition Control Register 28.2.29 NCMDQP : Normal Command Queue Port Register 28.2.30 NRSPQP : Normal Response Queue Port Register 28.2.31 NTDTBP0/NTDTBP0_BY : Normal Transfer Data Buffer Port Register 0 28.2.32 NIBIQP : Normal IBI Queue Port Register 28.2.33 NRSQP : Normal Receive Status Queue Port Register 28.2.34 NQTHCTL : Normal Queue Threshold Control Register 28.2.35 NTBTHCTL0 : Normal Transfer Data Buffer Threshold Control Register 0 28.2.36 NRQTHCTL : Normal Receive Status Queue Threshold Control Register 28.2.37 BST : Bus Status Register 28.2.38 BSTE : Bus Status Enable Register 28.2.39 BIE : Bus Interrupt Enable Register 28.2.40 BSTFC : Bus Status Force Register 28.2.41 NTST : Normal Transfer Status Register 28.2.42 NTSTE : Normal Transfer Status Enable Register 28.2.43 NTIE : Normal Transfer Interrupt Enable Register 28.2.44 NTSTFC : Normal Transfer Status Force Register 28.2.45 BCST : Bus Condition Status Register 28.2.46 SVST : Slave Status Register 28.2.47 DATBASm : Device Address Table Basic Register m (m = 0 to 3) 28.2.48 EXDATBAS : Extended Device Address Table Basic Register 28.2.49 SDATBASn : Slave Device Address Table Basic Register n (n = 0 to 2) 28.2.50 MSDCTm : Master Device Characteristic Table Register m (m = 0 to 3) 28.2.51 SVDCT : Slave Device Characteristic Table Register 28.2.52 SDCTPIDL : Slave Device Characteristic Table Provisional ID Low Register 28.2.53 SDCTPIDH : Slave Device Characteristic Table Provisional ID High Register 28.2.54 SVDVADn : Slave Device Address Register n (n = 0 to 2) 28.2.55 CSECMD : CCC Slave Events Command Register 28.2.56 CEACTST : CCC Enter Activity State Register 28.2.57 CMWLG : CCC Max Write Length Register 28.2.58 CMRLG : CCC Max Read Length Register 28.2.59 CETSTMD : CCC Enter Test Mode Register 28.2.60 CGDVST : CCC Get Device Status Register 28.2.61 CMDSPW : CCC Max Data Speed W (Write) Register 28.2.62 CMDSPR : CCC Max Data Speed R (Read) Register 28.2.63 CMDSPT : CCC Max Data Speed T (Turnaround) Register 28.2.64 CETSM : CCC Exchange Timing Support Information M (Mode) Register 28.2.65 BITCNT : Bit Count Register 28.2.66 NQSTLV : Normal Queue Status Level Register 28.2.67 NDBSTLV0 : Normal Data Buffer Status Level Register 0 28.2.68 NRSQSTLV : Normal Receive Status Queue Status Level Register 28.2.69 PRSTDBG : Present State Debug Register 28.2.70 MSERRCNT : Master Error Counters Register 28.3 Operation 28.3.1 Data Structures 28.3.1.1 Command Descriptor 28.3.1.2 Response Descriptor 28.3.1.3 IBI Status Descriptor 28.3.1.4 Receive Status Descriptor 28.3.2 Details of Function 28.3.2.1 Operation Mode 28.3.2.2 Data Handler 28.3.2.3 I2C/I3C Protocol 28.3.2.4 Error Detection 28.3.2.5 Other 28.3.3 Operation 28.3.3.1 Initial Setting Flow 28.3.3.2 I3C Communication Flow 28.3.3.3 Master Mode Communication Flow 28.3.3.4 Slave Mode Communication Flow 28.4 Interrupt Sources 28.4.1 Overview 28.4.2 Buffer Operation for Buffer Full/Empty Interrupts 28.5 Event Link Output 28.5.1 Interrupt Handling and Event Linking 28.6 Reset Descriptions 28.7 Usage Notes 28.7.1 Settings for the Operating Clock 29. Controller Area Network (CAN) Module 29.1 Overview 29.2 Register Descriptions 29.2.1 CTLR : Control Register 29.2.2 BCR : Bit Configuration Register 29.2.3 MKR[k] : Mask Register k (k = 0 to 7) 29.2.4 FIDCRk : FIFO Received ID Compare Register k (k = 0, 1) 29.2.5 MKIVLR : Mask Invalid Register 29.2.6 Mailbox Registers 29.2.6.1 MBj_ID : Mailbox ID Register j (j = 0 to 31) 29.2.6.2 MBj_DL : Mailbox Data Length Register j (j = 0 to 31) 29.2.6.3 MBj_Dm : Mailbox Data Register j (j = 0 to 31, m = 0 to 7) 29.2.6.4 MBj_TS : Mailbox Time Stamp Register j (j = 0 to 31) 29.2.7 MIER : Mailbox Interrupt Enable Register 29.2.8 MIER_FIFO : Mailbox Interrupt Enable Register for FIFO Mailbox Mode 29.2.9 MCTL_TX[j] : Message Control Register for Transmit (j = 0 to 31) 29.2.10 MCTL_RX[j] : Message Control Register for Receive (j = 0 to 31) 29.2.11 RFCR : Receive FIFO Control Register 29.2.12 RFPCR : Receive FIFO Pointer Control Register 29.2.13 TFCR : Transmit FIFO Control Register 29.2.14 TFPCR : Transmit FIFO Pointer Control Register 29.2.15 STR : Status Register 29.2.16 MSMR : Mailbox Search Mode Register 29.2.17 MSSR : Mailbox Search Status Register 29.2.18 CSSR : Channel Search Support Register 29.2.19 AFSR : Acceptance Filter Support Register 29.2.20 EIER : Error Interrupt Enable Register 29.2.21 EIFR : Error Interrupt Factor Judge Register 29.2.22 RECR : Receive Error Count Register 29.2.23 TECR : Transmit Error Count Register 29.2.24 ECSR : Error Code Store Register 29.2.25 TSR : Time Stamp Register 29.2.26 TCR : Test Control Register 29.3 Operation Modes 29.3.1 CAN Reset Mode 29.3.2 CAN Halt Mode 29.3.3 CAN Sleep Mode 29.3.4 CAN Operation Mode (Excluding Bus-Off State) 29.3.5 CAN Operation Mode (Bus-Off State) 29.4 Data Transfer Rate Configuration 29.4.1 Clock Setting 29.4.2 Bit Timing Setting 29.4.3 Data Transfer Rate 29.5 Mailbox and Mask Register Structure 29.6 Acceptance Filtering and Masking Functions 29.7 Reception and Transmission 29.7.1 Reception 29.7.2 Transmission 29.8 Interrupts 29.9 Usage Notes 29.9.1 Settings for the Module-Stop State 29.9.2 Settings for the Operating Clock 30. Serial Peripheral Interface (SPI) 30.1 Overview 30.2 Register Descriptions 30.2.1 SPCR : SPI Control Register 30.2.2 SSLP : SPI Slave Select Polarity Register 30.2.3 SPPCR : SPI Pin Control Register 30.2.4 SPSR : SPI Status Register 30.2.5 SPDR/SPDR_HA/SPDR_BY : SPI Data Register 30.2.6 SPBR : SPI Bit Rate Register 30.2.7 SPDCR : SPI Data Control Register 30.2.8 SPCKD : SPI Clock Delay Register 30.2.9 SSLND : SPI Slave Select Negation Delay Register 30.2.10 SPND : SPI Next-Access Delay Register 30.2.11 SPCR2 : SPI Control Register 2 30.2.12 SPCMD0 : SPI Command Register 0 30.3 Operation 30.3.1 Overview of SPI Operation 30.3.2 Controlling the SPI Pins 30.3.3 SPI System Configuration Examples 30.3.3.1 Single-master/single-slave with the MCU as a master 30.3.3.2 Single-master/single-slave with the MCU as a slave 30.3.3.3 Single-master/multi-slave with the MCU as a master 30.3.3.4 Single-master/multi-slave with the MCU as a slave 30.3.3.5 Multi-master/multi-slave with the MCU as a master 30.3.3.6 Master and slave in clock synchronous mode with the MCU configured as a master 30.3.3.7 Master and slave in clock synchronous mode with the MCU as a slave 30.3.4 Data Formats 30.3.4.1 Operation when parity is disabled (SPCR2.SPPE = 0) 30.3.4.2 Operation when parity is enabled (SPCR2.SPPE = 1) 30.3.5 Transfer Formats 30.3.5.1 When CPHA = 0 30.3.5.2 When CPHA = 1 30.3.6 Data Transfer Modes 30.3.6.1 Full-duplex synchronous serial communications (SPCR.TXMD = 0) 30.3.6.2 Transmit-Only Serial Communications (SPCR.TXMD = 1) 30.3.7 Transmit Buffer Empty and Receive Buffer Full Interrupts 30.3.8 Error Detection 30.3.8.1 Overrun errors 30.3.8.2 Parity errors 30.3.8.3 Mode fault errors 30.3.8.4 Underrun errors 30.3.9 Initializing the SPI 30.3.9.1 Initialization by clearing of the SPCR.SPE bit 30.3.9.2 Initialization by system reset 30.3.10 SPI Operation 30.3.10.1 Master mode operation 30.3.10.2 Slave mode operation 30.3.11 Clock Synchronous Operation 30.3.11.1 Master mode operation 30.3.11.2 Slave mode operation 30.3.12 Loopback Mode 30.3.13 Self-Diagnosis of Parity Bit Function 30.3.14 Interrupt Sources 30.4 Event Link Controller Event Output 30.4.1 Receive Buffer Full Event Output 30.4.2 Transmit Buffer Empty Event Output 30.4.3 Mode-Fault, Underrun, Overrun, or Parity Error Event Output 30.4.4 SPI Idle Event Output 30.4.5 Transmission-Completed Event Output 30.5 Usage Notes 30.5.1 Settings for the Module-Stop State 30.5.2 Constraint on Low-Power Functions 30.5.3 Constraints on Starting Transfer 30.5.4 Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output 30.5.5 Constraints on the SPSR.SPRF and SPSR.SPTEF Flags 31. Serial Interface UARTA (UARTA) 31.1 Overview 31.2 Register Descriptions 31.2.1 TXBAn : Transmit Buffer Register n (n = 0, 1) 31.2.2 RXBAn : Receive Buffer Register n (n = 0, 1) 31.2.3 ASIMAn0 : Operation Mode Setting Register n0 (n = 0, 1) 31.2.4 ASIMAn1 : Operation Mode Setting Register n1 (n = 0, 1) 31.2.5 BRGCAn : Baud Rate Generator Control Register n (n = 0, 1) 31.2.6 ASISAn : Status Register n (n = 0, 1) 31.2.7 ASCTAn : Status Clear Trigger Register n (n = 0, 1) 31.2.8 UTA0CK : UARTA Clock Select Register 0 31.2.9 UTA1CK : UARTA Clock Select Register 1 31.3 Operation 31.3.1 Operation Stop Mode 31.3.2 UART Mode 31.3.3 Receive Data Noise Filter 31.3.4 Baud Rate Generator 31.4 Usage Notes 31.4.1 Port Setting for RxDAn Pin 31.4.2 Point for Caution when Selecting the UARTAn Operation Clock (fUTAn) 31.4.3 Settings for the Module-Stop State 32. Serial Sound Interface Enhanced (SSIE) 32.1 Overview 32.2 Features 32.3 Block Diagram 32.4 Register Descriptions 32.4.1 SSICR : Control Register 32.4.2 SSISR : Status Register 32.4.3 SSIFCR : FIFO Control Register 32.4.4 SSIFSR : FIFO Status Register 32.4.5 SSIFTDR : Transmit FIFO Data Register 32.4.6 SSIFRDR : Receive FIFO Data Register 32.4.7 SSIOFR : Audio Format Register 32.4.8 SSISCR : Status Control Register 32.5 Communication Formats 32.5.1 I2S Format 32.5.2 Monaural Format 32.5.2.1 Short frame 32.5.2.2 Long frame 32.5.3 TDM Format 32.6 Communication Modes 32.6.1 Slave-mode Communication 32.6.2 Master-mode Communication 32.6.3 Transmission 32.6.4 Reception 32.6.5 Transmission and Reception 32.7 Operation 32.7.1 Idle State 32.7.2 Communication States 32.7.2.1 Data communication state 32.7.2.2 Padding communication 32.8 Communication Operation 32.8.1 Start Communication 32.8.2 Transmission 32.8.3 Reception 32.8.4 Transmission and Reception 32.8.5 Halt Communication 32.8.6 Error Handling 32.8.7 Resume Communication 32.9 Interrupts 32.9.1 SSIE0_SSIF Interrupt 32.9.2 SSIE0_SSITXI Interrupt 32.9.3 SSIE0_SSIRXI Interrupt 32.10 Software Resets 32.10.1 Software Reset Procedure 32.11 Notes 32.11.1 Notes for Slave-mode Communication 32.11.1.1 SSIBCK0 control 32.11.1.2 SSILRCK0/SSIFS0 pin 32.11.2 Notes for Master-mode Communication 32.11.2.1 AUCKE control 32.11.2.2 LRCONT control 32.11.2.3 BCKASTP control 32.11.3 Notes for Communication Flow 32.11.3.1 When an error interrupt is generated 32.11.3.2 Transmit data empty interrupt 32.11.3.3 Receive data full interrupt 32.11.3.4 Switching transfer modes 32.11.3.5 Resume communication after halting SSIE 32.11.4 Write Access Restriction 32.11.4.1 SSICR register 32.11.4.2 SSISR register 32.11.4.3 Communication state 33. Cyclic Redundancy Check (CRC) 33.1 Overview 33.2 Register Descriptions 33.2.1 CRCCR0 : CRC Control Register 0 33.2.2 CRCCR1 : CRC Control Register 1 33.2.3 CRCDIR/CRCDIR_BY : CRC Data Input Register 33.2.4 CRCDOR/CRCDOR_HA/CRCDOR_BY : CRC Data Output Register 33.2.5 CRCSAR : Snoop Address Register 33.3 Operation 33.3.1 Basic Operation 33.3.2 CRC Snoop Function 33.4 Usage Notes 33.4.1 Settings for the Module-Stop State 33.4.2 Note on Transmission 34. 12-Bit A/D Converter (ADC12) 34.1 Overview 34.2 Register Descriptions 34.2.1 ADDRn : A/D Data Registers n (n = 0 to 10, 17 to 22) 34.2.2 ADDBLDR : A/D Data Duplexing Register 34.2.3 ADDBLDRn : A/D Data Duplexing Register n (n = A, B) 34.2.4 ADTSDR : A/D Temperature Sensor Data Register 34.2.5 ADOCDR : A/D Internal Reference Voltage Data Register 34.2.6 ADRD : A/D Self-Diagnosis Data Register 34.2.7 ADCSR : A/D Control Register 34.2.8 ADANSA0 : A/D Channel Select Register A0 34.2.9 ADANSA1 : A/D Channel Select Register A1 34.2.10 ADANSB0 : A/D Channel Select Register B0 34.2.11 ADANSB1 : A/D Channel Select Register B1 34.2.12 ADADS0 : A/D-Converted Value Addition/Average Channel Select Register 0 34.2.13 ADADS1 : A/D-Converted Value Addition/Average Channel Select Register 1 34.2.14 ADADC : A/D-Converted Value Addition/Average Count Select Register 34.2.15 ADCER : A/D Control Extended Register 34.2.16 ADSTRGR : A/D Conversion Start Trigger Select Register 34.2.17 ADEXICR : A/D Conversion Extended Input Control Registers 34.2.18 ADSSTRn/ADSSTRL/ADSSTRT/ADSSTRO : A/D Sampling State Register (n = 0 to 10) 34.2.19 ADDISCR : A/D Disconnection Detection Control Register 34.2.20 ADACSR : A/D Conversion Operation Mode Select Register 34.2.21 ADGSPCR : A/D Group Scan Priority Control Register 34.2.22 ADCMPCR : A/D Compare Function Control Register 34.2.23 ADCMPANSR0 : A/D Compare Function Window A Channel Select Register 0 34.2.24 ADCMPANSR1 : A/D Compare Function Window A Channel Select Register 1 34.2.25 ADCMPANSER : A/D Compare Function Window A Extended Input Select Register 34.2.26 ADCMPLR0 : A/D Compare Function Window A Comparison Condition Setting Register 0 34.2.27 ADCMPLR1 : A/D Compare Function Window A Comparison Condition Setting Register 1 34.2.28 ADCMPLER : A/D Compare Function Window A Extended Input Comparison Condition Setting Register 34.2.29 ADCMPDRn : A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register (n = 0, 1) 34.2.30 ADWINnLB : A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register (n = L, U) 34.2.31 ADCMPSR0 : A/D Compare Function Window A Channel Status Register 0 34.2.32 ADCMPSR1 : A/D Compare Function Window A Channel Status Register1 34.2.33 ADCMPSER : A/D Compare Function Window A Extended Input Channel Status Register 34.2.34 ADCMPBNSR : A/D Compare Function Window B Channel Select Register 34.2.35 ADCMPBSR : A/D Compare Function Window B Status Register 34.2.36 ADWINMON : A/D Compare Function Window A/B Status Monitor Register 34.2.37 ADHVREFCNT : A/D High-Potential/Low-Potential Reference Voltage Control Register 34.3 Operation 34.3.1 Scanning Operation 34.3.2 Single Scan Mode 34.3.2.1 Basic Operation 34.3.2.2 Channel Selection and Self-Diagnosis 34.3.2.3 A/D Conversion of Temperature Sensor Output or Internal Reference Voltage 34.3.2.4 A/D Conversion in Double-Trigger Mode 34.3.2.5 Extended Operations When Double-Trigger Mode Is Selected 34.3.3 Continuous Scan Mode 34.3.3.1 Basic Operation 34.3.3.2 Channel Selection and Self-Diagnosis 34.3.4 Group Scan Mode 34.3.4.1 Basic Operation 34.3.4.2 A/D Conversion in Double-Trigger Mode 34.3.4.3 Group Priority Operation 34.3.5 Compare Function for Windows A and B 34.3.5.1 Compare Function Windows A and B 34.3.5.2 Event Output of Compare Function 34.3.5.3 Restrictions on Compare Function 34.3.6 Analog Input Sampling and Scan Conversion Time 34.3.7 Usage Example of A/D Data Register Automatic Clearing Function 34.3.8 A/D-Converted Value Addition/Average Mode 34.3.9 Disconnection Detection Assist Function 34.3.10 Starting A/D Conversion with an Asynchronous Trigger 34.3.11 Starting A/D Conversion with a Synchronous Trigger from a Peripheral Module 34.4 Interrupt Sources and DTC Transfer Requests 34.4.1 Interrupt Requests 34.5 Event Link Function 34.5.1 Event Output to the ELC 34.5.2 ADC12 Operation through an Event from the ELC 34.6 Selecting Reference Voltage 34.7 A/D Conversion Procedure When Selecting Internal Reference Voltage as High-Potential Reference Voltage 34.8 Usage Notes 34.8.1 Constraints on Setting the Registers 34.8.2 Constraints on Reading the Data Registers 34.8.3 Constraints on Stopping A/D Conversion 34.8.4 A/D Conversion Restart and Termination Timing 34.8.5 Constraints on Scan End Interrupt Handling 34.8.6 Settings for the Module-Stop Function 34.8.7 Notes on Entering the Low-Power States 34.8.8 Error in Absolute Accuracy When Disconnection Detection Assistance Is in Use 34.8.9 ADHSC Bit Rewriting Procedure 34.8.10 Constraints on Operating Modes and Status Bits 34.8.11 Notes on Board Design 34.8.12 Constraints on Noise Prevention 34.8.13 Port Settings When Using the ADC12 Input 34.8.14 Notes on Canceling Software Standby Mode 35. Temperature Sensor (TSN) 35.1 Overview 35.2 Register Descriptions 35.2.1 TSCDR : Temperature Sensor Calibration Data Register 35.3 Using the Temperature Sensor 35.3.1 Preparation for Using the Temperature Sensor 35.3.2 Procedures for Using the Temperature Sensor 36. Data Operation Circuit (DOC) 36.1 Overview 36.2 DOC Register Descriptions 36.2.1 DOCR : DOC Control Register 36.2.2 DODIR : DOC Data Input Register 36.2.3 DODSR : DOC Data Setting Register 36.3 Operation 36.3.1 Data Comparison Mode 36.3.2 Data Addition Mode 36.3.3 Data Subtraction Mode 36.4 Interrupt Source 36.5 Output of an Event Signal to the Event Link Controller (ELC) 36.6 Usage Notes 36.6.1 Settings for the Module-Stop State 37. SRAM 37.1 Overview 37.2 Register Descriptions 37.2.1 PARIOAD : SRAM Parity Error Operation After Detection Register 37.2.2 SRAMPRCR : SRAM Protection Register 37.2.3 Trace Control (for the MTB) 37.2.4 CoreSight(TM) (for MTB) 37.3 Operation 37.3.1 Parity Calculation Function 37.3.2 SRAM Error Sources 37.3.3 Access Cycle 37.3.4 Low-Power Function 37.4 Usage Notes 37.4.1 Instruction Fetch from the SRAM Area 37.4.2 SRAM Store Buffer 38. Flash Memory 38.1 Overview 38.2 Memory Structure 38.3 Register Descriptions 38.3.1 DFLCTL : Data Flash Control Register 38.3.2 PFBER : Prefetch Buffer Enable Register 38.3.3 FENTRYR : Flash P/E Mode Entry Register 38.3.4 FPR : Protection Unlock Register 38.3.5 FPSR : Protection Unlock Status Register 38.3.6 FPMCR : Flash P/E Mode Control Register 38.3.7 FISR : Flash Initial Setting Register 38.3.8 FRESETR : Flash Reset Register 38.3.9 FASR : Flash Area Select Register 38.3.10 FCR : Flash Control Register 38.3.11 FEXCR : Flash Extra Area Control Register 38.3.12 FSARH : Flash Processing Start Address Register H 38.3.13 FSARL : Flash Processing Start Address Register L 38.3.14 FEARH : Flash Processing End Address Register H 38.3.15 FEARL : Flash Processing End Address Register L 38.3.16 FWBL0 : Flash Write Buffer Register L0 38.3.17 FWBH0 : Flash Write Buffer Register H0 38.3.18 FRBL0 : Flash Read Buffer Register L0 38.3.19 FRBH0 : Flash Read Buffer Register H0 38.3.20 FSTATR1 : Flash Status Register 1 38.3.21 FSTATR2 : Flash Status Register 2 38.3.22 FEAMH : Flash Error Address Monitor Register H 38.3.23 FEAML : Flash Error Address Monitor Register L 38.3.24 FSCMR : Flash Start-Up Setting Monitor Register 38.3.25 FAWSMR : Flash Access Window Start Address Monitor Register 38.3.26 FAWEMR : Flash Access Window End Address Monitor Register 38.3.27 UIDR2n : Unique ID Registers 2n (n = 0 to 3) 38.3.28 PNR2n : Part Numbering Register 2n (n = 0 to 3) 38.3.29 MCUVER2 : MCU Version Register 2 38.4 Instruction Prefetch from Flash Memory 38.5 Operating Modes Associated with the Flash Memory 38.5.1 ID Code Protection 38.6 Overview of Functions 38.6.1 Configuration Area Bit Map 38.6.2 Startup Area Select 38.6.3 Protection by Access Window 38.7 Programming Commands 38.8 Suspend Operation 38.9 Protection 38.9.1 Startup Program Protection 38.9.2 Area Protection 38.10 Serial Programming Mode 38.10.1 SCI Boot Mode and IIC Boot Mode 38.11 Using a Serial Programmer 38.11.1 Serial Programming 38.12 Self-Programming 38.12.1 Overview 38.12.2 Background Operation 38.13 Programming and Erasure 38.13.1 Sequencer Modes 38.13.1.1 Data Flash Access Disable Mode 38.13.1.2 Read Mode 38.13.1.3 P/E Modes 38.13.2 Software Commands 38.13.3 Software Command Usage 38.14 Reading the Flash Memory 38.14.1 Reading the Code Flash Memory 38.14.2 Reading the Data Flash Memory 38.15 Usage Notes 38.15.1 Erase Suspended Area 38.15.2 Constraints on Additional Writes 38.15.3 Reset during Programming and Erasure 38.15.4 Non-Maskable Interrupt Disabled during Programming and Erasure 38.15.5 Location of Interrupt Vectors during Programming and Erasure 38.15.6 Programming and Erasure in Subosc-Speed Operating Mode 38.15.7 Abnormal Termination during Programming and Erasure 38.15.8 Actions Prohibited during Programming and Erasure 38.15.9 Flash-IF clock (ICLK) during Program/Erase 39. True Random Number Generator (TRNG) 39.1 Overview 40. Internal Voltage Regulator 40.1 Overview 40.2 Operation 41. Electrical Characteristics 41.1 Absolute Maximum Ratings 41.2 DC Characteristics 41.2.1 Tj/Ta Definition 41.2.2 I/O VIH, VIL 41.2.3 I/O IOH, IOL 41.2.4 I/O VOH, VOL, and Other Characteristics 41.2.5 Operating and Standby Current 41.2.6 VCC Rise and Fall Gradient and Ripple Frequency 41.2.7 Thermal Characteristics 41.3 AC Characteristics 41.3.1 Frequency 41.3.2 Clock Timing 41.3.3 Reset Timing 41.3.4 Wakeup Time 41.3.5 NMI and IRQ Noise Filter 41.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 41.3.7 CAC Timing 41.3.8 SCI Timing 41.3.9 SPI Timing 41.3.10 I3C Timing 41.3.11 SSIE Timing 41.3.12 UARTA Timing 41.3.13 CLKOUT Timing 41.4 USB Characteristics 41.4.1 USBFS Timing 41.4.2 USBCC Characteristics 41.5 ADC12 Characteristics 41.6 TSN Characteristics 41.7 OSC Stop Detect Characteristics 41.8 POR and LVD Characteristics 41.9 Flash Memory Characteristics 41.9.1 Code Flash Memory Characteristics 41.9.2 Data Flash Memory Characteristics 41.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History Colophon Back Cover