Datasheet CT4022 (Allegro) - 3
| 制造商 | Allegro |
| 描述 | Isolated, 500kHz TMR Current Sensor in 1 mΩ SOIC-8 Package |
| 页数 / 页 | 5 / 3 — XtremeSense™ TMR Current Sensor. CT4022 and CT4032. with High dV/dt … |
| 文件格式/大小 | PDF / 775 Kb |
| 文件语言 | 英语 |
XtremeSense™ TMR Current Sensor. CT4022 and CT4032. with High dV/dt Immunity and Common-Mode Field Rejection
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XtremeSense™ TMR Current Sensor CT4022 and CT4032 with High dV/dt Immunity and Common-Mode Field Rejection PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use
(reference Allegro DWG-0000385, Rev. 2 or JEDEC MS-012AA) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 8° 4.90 BSC 0° 0.65 1.27 8 8 0.21 ±0.04 3.90 BSC 6.00 BSC 5.60 A 1.75 1 2 +0.43 1 2 0.84 –0.44 D 2.01 C PCB Layout Reference View 0.25 BSC SEATING PLANE Branded Face GAUGE PLANE C 8× +0.13 XXXXXXXX 0.10 C 1.62 –0.27 SEATING A YYWW PLANE Lot Number 0.41 ±0.10 +0.10 0.15 –0.05 1.27 BSC 1 A Terminal #1 mark area B Standard Branding Reference View Line 1, 2: Max. 8 characters per line B Branding scale and appearance at supplier discretion Belly Brand: 4 characters C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); Line 1: Allegro Part Number all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary Line 2: Logo A, Allegro 4 Digit Date Code (YYWW) to meet application process requirements and PCB layout tolerances. Line 3: Characters 5, 6, 7, 8 of Allegro Assembly Lot Number
Figure 2: SOIC-8 Package Drawing and Dimensions
3 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
(reference Allegro DWG-0000385, Rev. 2 or JEDEC MS-012AA) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 8° 4.90 BSC 0° 0.65 1.27 8 8 0.21 ±0.04 3.90 BSC 6.00 BSC 5.60 A 1.75 1 2 +0.43 1 2 0.84 –0.44 D 2.01 C PCB Layout Reference View 0.25 BSC SEATING PLANE Branded Face GAUGE PLANE C 8× +0.13 XXXXXXXX 0.10 C 1.62 –0.27 SEATING A YYWW PLANE Lot Number 0.41 ±0.10 +0.10 0.15 –0.05 1.27 BSC 1 A Terminal #1 mark area B Standard Branding Reference View Line 1, 2: Max. 8 characters per line B Branding scale and appearance at supplier discretion Belly Brand: 4 characters C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); Line 1: Allegro Part Number all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary Line 2: Logo A, Allegro 4 Digit Date Code (YYWW) to meet application process requirements and PCB layout tolerances. Line 3: Characters 5, 6, 7, 8 of Allegro Assembly Lot Number
Figure 2: SOIC-8 Package Drawing and Dimensions
3 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com