Datasheet MAX5362 (Analog Devices) - 9

Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362
SDA t t BUF SU, DAT tSU, STA tHD, STA t t LOW tHD, DAT SU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 3. Two-Wire Serial Interface Timing Diagram
Shutdown Mode
VDD The MAX5360/MAX5361/MAX5362 include a software- controlled shutdown mode that reduces the supply cur- μC rent to <1µA. All internal circuitry is disabled and an SDA SCL internal 10kΩ resistor is placed from OUT to GND to SCL VDD ensure 0V at OUT while in shutdown. The device enters RS* MAX5360M shutdown in less than 5µs and exits shutdown in less 2V REFERENCE than 50µs. SDA OUT OFFSET ADJUSTMENT
Digital Section Serial interface
SCL VDD The MAX5360/MAX5361/MAX5362 use a simple two- wire serial interface requiring only two I/O lines (two- MAX5361N 4V REFERENCE wire bus) of a standard microprocessor (µP) port. SDA OUT THRESHOLD ADJUSTMENT Figure 3 shows the timing diagram for signals on the 2- wire bus. The two bus lines (SDA and SCL) must be high when SCL VDD the bus is not in use. The MAX5360/MAX5361/ MAX5362P MAX5362 are receive-only devices (slaves) and must VDD REFERENCE be controlled by a bus master device. Figure 4 shows a SDA OUT GAIN ADJUSTMENT typical application where multiple devices can be con- nected to the bus provided they have different address RS* IS OPTIONAL. settings. External pullup resistors are not necessary on these lines (when driven by push-pull drivers), though Figure 4. Typical Application Circuit the MAX5360/MAX5361/MAX5362 can be used in applications where pullup resistors are required (such
Power-On Reset
as in I2C systems) to maintain compatibility with exist- The MAX5360/MAX5361/MAX5362 have a power-on ing circuitry. The serial interface operates at SCL rates reset circuit to set the DAC’s output to 0 when V up to 400kHz. The SDA state is allowed to change only DD is first applied or when V while SCL is low, with the exception of START and DD dips below 1.7V. This ensures that unwanted DAC output voltages will not occur STOP conditions as shown in Figure 5. Each transmis- immediately following a system startup, such as after a sion consists of a START condition sent by the bus loss of power. The output glitch on startup is typically master device, followed by the MAX5360/MAX5361/ <50mV. MAX5362’s preset slave address, a power-mode bit, the DAC data (6 bits + 2 subbits), and finally, a STOP
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