Datasheet AH4930Q (Diodes) - 5
| 制造商 | Diodes |
| 描述 | Automotive 3D Magnetic Linear Hall Sensor with I2C Interface |
| 页数 / 页 | 23 / 5 — AH4930Q. Electrical Characteristics. Timing Requirements for I2C:. 400kHz … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
AH4930Q. Electrical Characteristics. Timing Requirements for I2C:. 400kHz (Fast Mode). 1000kHz (Fast Mode+). Symbol. Parameter. Unit
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AH4930Q Electrical Characteristics
(VDD = 3.3V @TA = +25°C, unless otherwise specified.) (continued)
Timing Requirements for I2C: 400kHz (Fast Mode) 1000kHz (Fast Mode+) Symbol Parameter Unit Min Typ Max Min Typ Max
fSCL I2C Clock Frequency — — 400 — — 1000 kHz tL Clock Low Time 1.3 — — 0.5 — — µs tH Clock High Time 0.6 — — 0.4 — — µs Hold Time for a (Repeated) START tSTA 0.6 — — 0.4 — — µs Condition tSTOP Setup Time for STOP Condition 0.6 — — 0.4 — — µs tSU Data Setup Time 0.1 — — 0.1 — — µs tHOLD Data Hold Time 0 — — 0 — — µs tRISE Rise Time of SDA and SCL (Note 9) — — 0.5 — — 0.5 µs tFALL Fall Time of SDA and SCL (Note 9) — — 0.3 — 0.25 0.3 µs Bus Free Time Between a STOP and a tWAIT 0.6 — — 0.4 — — µs START Condition Note: 9. Dependent on used R-C combination. For applications, total capacitive load should be < 200pF.
t t t t RISE FALL FALL tRISE STOP tWAIT t t STA tSU tHOLD H tL SDA SCL STOP START R/W BIT R/W BIT R/W BIT Figure 1. I2C Timing Parameters
AH4930Q 5 of 23 April 2025 Document number: DS45843 Rev. 2 - 2
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© 2025 Copyright Diodes Incorporated. All Rights Reserved.
(VDD = 3.3V @TA = +25°C, unless otherwise specified.) (continued)
Timing Requirements for I2C: 400kHz (Fast Mode) 1000kHz (Fast Mode+) Symbol Parameter Unit Min Typ Max Min Typ Max
fSCL I2C Clock Frequency — — 400 — — 1000 kHz tL Clock Low Time 1.3 — — 0.5 — — µs tH Clock High Time 0.6 — — 0.4 — — µs Hold Time for a (Repeated) START tSTA 0.6 — — 0.4 — — µs Condition tSTOP Setup Time for STOP Condition 0.6 — — 0.4 — — µs tSU Data Setup Time 0.1 — — 0.1 — — µs tHOLD Data Hold Time 0 — — 0 — — µs tRISE Rise Time of SDA and SCL (Note 9) — — 0.5 — — 0.5 µs tFALL Fall Time of SDA and SCL (Note 9) — — 0.3 — 0.25 0.3 µs Bus Free Time Between a STOP and a tWAIT 0.6 — — 0.4 — — µs START Condition Note: 9. Dependent on used R-C combination. For applications, total capacitive load should be < 200pF.
t t t t RISE FALL FALL tRISE STOP tWAIT t t STA tSU tHOLD H tL SDA SCL STOP START R/W BIT R/W BIT R/W BIT Figure 1. I2C Timing Parameters
AH4930Q 5 of 23 April 2025 Document number: DS45843 Rev. 2 - 2
www.diodes.com
© 2025 Copyright Diodes Incorporated. All Rights Reserved.