Datasheet VNF1048F (STMicroelectronics) - 9

VNF1048F Main electrical characteristics ID Symbol Parameter Test conditions Min. Typ. Max. Unit
CGATE = 80 nF Full VGS to VGS < 0.5 5.7 tOFF Gate turn off 2.6 µs CGATE = 80 nF Gate under voltage 5.8 VGS_UVLO_6V V lockout S = 6 V 5 V Gate under voltage 5.9 VGS_UVLO_10V V lockout S >10 V 8.5 V Enable at Charge Pump startup if Ext Gate under voltage 5.10 VG_UVLO_BLK FET turn-on is required, and applied - 6 % 100 + 6 % µs lockout blanking after CP_LOW expiration (falling edge) Gate under voltage 5.11 VG_UVLO_DEGLITCH lockout de-glitch filtering - 15 % 8 + 15 % µs time 5.12 QGMAX Maximum gate charge VGS = 10 V 800 nC
Table 13. Current sense amplifier with integrated ADC ID Symbol Parameter Test conditions Min. Typ. Max. Unit
Common-mode input voltage 6.1 VSENSE_CM 0 70 V range Differential input voltage full 6.2 VSENSE_FSR 0 160 mV scale range 6.3 I_SENSE_P CSA positive input current 400 μA 6.4 I_SENSE_N CSA negative input current 560 μA Current Sense ADC Full scale V 6.5 V SENSE_ADC[12:0] = SENSE_ADC_CONV 0 8191 range resolution MIN((VSENSE/160 * 8192), 8191) Current Sense ADC sample 6.6 VSENSE_REFRESH 2.4 kSample/s rate 6.7 VSENSE_ACC_6mV 6 mV < VSENSE_DIFF < 10 mV -10 +10 % 6.8 VSENSE_ACC_10mV VSENSE_DIFF = 10 mV -5 +5 % Digital Current Sense Accuracy 6.9 VSENSE_ACC_20mV VSENSE_DIFF > 20 mV -3 +3 % 6.10 VSENSE_ACC_1.8mV 1.8 mV < VSENSE_DIFF < 6 mV -17 +17 %
Table 14. External FET VDS Protection ID Symbol Parameter Test conditions Min. Typ. Max. Unit
VDS monitor threshold range 7.1 VDS_THRS_RANGE 300 1800 mV 31 steps adjustable through SPI 7.2 VDS_THRS_STEP VDS monitor threshold step 50 mV VDS_THRS_0 300 VDS_THRS_ 1 350 VDS_THRS_2 400 7.3 VDS monitor thresholds mV VDS_THRS_3 450 VDS_THRS_ 4 500 VDS_THRS_ 5 550
DS13084
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Rev 6 page 9/52
Document Outline 1 Block diagram and pin description 2 Electrical specification 2.1 Absolute maximum ratings 2.2 Thermal data 2.3 Main electrical characteristics 3 eFuse function 4 Self Test 4.1 Current Sense Self Test 4.2 External FET VDS Detection Self Test 4.3 External FET Stuck-on Self Test 5 Protections 5.1 Battery undervoltage shutdown 5.2 Device overtemperature shutdown 5.3 External MOSFET overtemperature shutdown 5.4 External MOSFET desaturation shut-down 5.5 Hard short circuit latch-off 5.6 Current vs time latch-off 5.7 Low Current Bypass desaturation shut-down 6 SPI functional description 6.1 SPI Communication 6.2 Signal description 6.3 SPI protocol 6.4 Operating code definition 6.5 Write mode 6.6 Read mode 6.7 Read and clear status command 6.8 SPI device information 6.9 Special commands 6.10 Global status byte 6.11 Address map 6.12 ROM memory map 6.13 Control registers 6.14 Status registers 6.15 Timeout watchdog 7 Operating modes 7.1 State Diagram 7.2 PowerON mode 7.3 Stand-by mode 7.4 WakeUp mode 7.5 Unlocked mode 7.6 Locked mode 7.7 Self-test mode 8 Application information 9 Package information 9.1 QFN32L 5x5 package information Revision history