Datasheet BlueNRG-LPS (STMicroelectronics) - 6

BlueNRG-LPS Arm® Cortex®-M0+ core with MPU 1.2 Arm® Cortex®-M0+ core with MPU
The BlueNRG-LPS contains an Arm® Cortex®-M0+ microcontroller core. The Arm® Cortex®-M0+ was developed to provide a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M0+ can run from 1 MHz up to 64 MHz. The Arm® Cortex®-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The interrupts are handled by the Arm® Cortex®-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls specific Arm® Cortex®-M0+ interrupts as well as the BlueNRG-LPS peripheral interrupts. With its embedded ARM core, the BlueNRG-LPS family is compatible with all ARM tools and software.
1.3 Memories 1.3.1 Embedded Flash memory
The Flash controller implements the erase and program Flash memory operation. The flash controller also implements the read and write protection. The Flash memory features are: • Memory organization: – 1 bank of 192 kB – Page size: 2 kB – Page number 96 • 32-bit wide data read/write • Page erase and mass erase The Flash controller features are: • Flash memory read operations: single read or mass read • Flash memory write operations: single data write or 4x32-bits burst write or mass write • Flash memory erase operations: page erase or mass erase • Page write protect mechanism: 4 variable-size memory segments
1.3.2 Embedded SRAM
The BlueNRG-LPS has a total of 24 kB of embedded SRAM, split into two banks as shown in the following table:
Table 1. SRAM overview SRAM bank Size Address Retained in DEEPSTOP
SRAM0 12 kB 0x2000 0000 Always SRAM1 12 kB 0x2000 3000 Programmable by the user
1.3.3 Embedded ROM
The BlueNRG-LPS has a total of 7 kB of embedded ROM. This area is ST reserved and contains: • The UART bootloader from which the CPU boots after each reset (first 6 kB of ROM memory) • Some ST reserved values including the ADC trimming values (the last 1 kB of ROM memory)
1.3.4 Embedded OTP
The one-time-programmable (OTP) is a memory of 1 kB dedicated for user data. The OTP data cannot be erased. The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a system reset. This operation freezes the OTP memory from further unwanted write operations.
DS13819
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Rev 2 page 6/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history