Datasheet BlueNRG-LPS (STMicroelectronics) - 2

制造商STMicroelectronics
描述Programmable Bluetooth Low Energy Wireless SoC
页数 / 页63 / 2 — BlueNRG-LPS. DS13819. Rev 2. page 2/63
文件格式/大小PDF / 8.2 Mb
文件语言英语

BlueNRG-LPS. DS13819. Rev 2. page 2/63

BlueNRG-LPS DS13819 Rev 2 page 2/63

该数据表的模型线

文件文字版本

BlueNRG-LPS
• Clock sources – 64 MHz PLL – Fail safe 32 MHz crystal oscillator with integrated trimming capacitors – 32 kHz crystal oscillator – Internal low-power 32 kHz RO • On-chip non-volatile Flash memory of 192 kB • On-chip RAM of 24 kB + 4 kB PKA RAM • One-time-programmable (OTP) memory area of 1 kB • Embedded UART bootloader • Ultra-low power modes with or without timer and RAM retention • Quadrature decoder • Enhanced security mechanisms such as: – Flash read/write protection – SWD disabling – Secure bootloader • Security features – True random number generator (RNG) – Hardware encryption AES maximum 128-bit security co-processor – HW public key accelerator (PKA) – Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p) – CRC calculation unit – 64-bit unique ID • System peripherals – 1x DMA controller with 8 channels supporting ADC, SPI-I2S, I2C, USART, LPUART, TIMERS – 1x SPI with I2S interface multiplexed – 1x I2C (SMBus/PMBus) – 1x LPUART (low power) – 1x USART (ISO 7816 smartcard mode, IrDA, SPI Master and Modbus) – 1x independent WDG – 1x real-time clock (RTC) – 1x independent SysTick – 1x 16-bits, four channel general purpose timer – 2x 16-bits, two channel general purpose timer – Infrared interface • Up to 20 fast I/Os – All of them with wake-up capability – All of them retain state in low-power – All of them 5 V tolerant • Analog peripherals – 12-bit ADC with 8 input channels, up to 16 bits with down sampler – Battery monitoring – Analog watchdog • Development support – Serial wire debug (SWD) – 4 breakpoints and 2 watchpoints • All packages are ECOPACK2 compliant
DS13819
-
Rev 2 page 2/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history