Datasheet PIC16F18056, PIC16F18076 (Microchip) - 4
| 制造商 | Microchip |
| 描述 | PIC16F18056/76 Full-Featured, 28/40-Pin Microcontrollers |
| 页数 / 页 | 565 / 4 — PIC16F18056/76. Analog Peripherals. Preliminary Datasheet |
| 文件格式/大小 | PDF / 8.5 Mb |
| 文件语言 | 英语 |
PIC16F18056/76. Analog Peripherals. Preliminary Datasheet
该数据表的模型线
- PIC16F18876-E/ML PIC16F18876-E/MV PIC16F18876-E/P PIC16F18876-E/PT PIC16F18876-I/ML PIC16F18876-I/MV PIC16F18876-I/P PIC16F18876-I/PT PIC16F18876T-E/PT PIC16F18876T-E/PTVAO PIC16F18876T-I/ML PIC16F18876T-I/MV PIC16F18876T-I/MVC02 PIC16F18876T-I/MVVAO PIC16F18876T-I/PT PIC16LF18876-E/ML PIC16LF18876-E/MV PIC16LF18876-E/P PIC16LF18876-E/PT PIC16LF18876-I/ML PIC16LF18876-I/MV PIC16LF18876-I/P PIC16LF18876-I/PT PIC16LF18876T-I/ML PIC16LF18876T-I/MV PIC16LF18876T-I/PT
文件文字版本
PIC16F18056/76
• One Configurable 8/16-Bit Timer (TMR0) • Two 16-Bit Timers (TMR1/3) with Gate Control • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) • One Numerically Controlled Oscillator (NCO): – Generates true linear frequency control and increased frequency resolution – Input clock up to 64 MHz • Up to Two Enhanced Universal Synchronous Asynchronous Receiver Transmitters (EUSART): – RS-232, RS-485, and LIN compatible – Auto wake-up on Start • Up to Two Host Synchronous Serial Ports (MSSP): – Serial Peripheral Interface (SPI) mode: • Client select synchronization – Inter-Integrated Circuit (I2C) mode: • 7/10-bit Addressing modes • Peripheral Pin Select (PPS): – Enables pin mapping of digital I/O • Device I/O Port Features: – Up to 35 I/O pins – One input-only pin – Individual I/O direction, open-drain, input threshold, slew rate, and weak pull-up control – Interrupt-on-Change (IOC) on up to 25 pins – One external interrupt pin
Analog Peripherals
• Analog-to-Digital Converter with Computation (ADCC): – 10-bit resolution – Up to 35 external input channels – Four internal input channels – Internal ADC oscillator (ADCRC) – Operates in Sleep – Selectable auto-conversion trigger sources • Charge Pump Module: – Improves accuracy of analog modules at low voltages • 8-Bit Digital-to-Analog Converter (DAC): – Output available on one I/O pin – Internal connections to ADC and Comparators • One Comparator (CMP): – Up to four external inputs – Configurable output polarity – External output via Peripheral Pin Select • Zero-Cross Detect (ZCD): – Detect when AC signal on pin crosses ground • Two Fixed Voltage References (FVR): – Selectable 1.024V, 2.048V, and 4.096V output levels – FVR1 internally connected to ADC – FVR2 internally connected to Comparator © 2021-2022 Microchip Technology Inc.
Preliminary Datasheet
DS40002325B-page 4 and its subsidiaries Document Outline Introduction PIC16F180 Family Summary Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Block Diagram Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables 4. Guidelines for Getting Started with PIC16F180 Microcontrollers 4.1. Basic Connection Requirements 4.2. Power Supply Pins 4.2.1. Decoupling Capacitors 4.2.2. Tank Capacitors 4.3. Master Clear (MCLR) Pin 4.4. In-Circuit Serial Programming™ (ICSP™) Pins 4.5. Unused I/Os 5. Register and Bit Naming Conventions 5.1. Register Names 5.2. Bit Names 5.2.1. Short Bit Names 5.2.2. Long Bit Names 5.2.3. Bit Fields 5.3. Register and Bit Naming Exceptions 5.3.1. Status, Interrupt and Mirror Bits 6. Register Legend 7. Enhanced Mid-Range CPU 7.1. Automatic Interrupt Context Saving 7.2. 16-Level Stack with Overflow and Underflow 7.3. File Select Registers 7.4. Instruction Set 8. Device Configuration 8.1. Configuration Words 8.2. Code Protection 8.3. Write Protection 8.4. User ID 8.5. Device ID and Revision ID 8.6. Register Definitions: Configuration Settings 8.6.1. CONFIG1 8.6.2. CONFIG2 8.6.3. CONFIG3 8.6.4. CONFIG4 8.6.5. CONFIG5 8.7. Register Definitions: Device ID and Revision ID 8.7.1. Device ID 8.7.2. Revision ID 9. Memory Organization 9.1. Program Memory Organization 9.1.1. Reading Program Memory as Data 9.1.1.1. RETLW Instruction 9.1.1.2. Indirect Read with FSR 9.1.2. Memory Access Partition (MAP) 9.1.2.1. Application Block 9.1.2.2. Boot Block 9.1.2.3. Storage Area Flash 9.1.2.4. Memory Write Protection 9.1.2.5. Memory Violation 9.1.3. Device Information Area (DIA) 9.1.3.1. Microchip Unique Identifier (MUI) 9.1.3.2. External Unique Identifier (EUI) 9.1.3.3. Standard Parameters for the Temperature Sensor 9.1.3.4. Fixed Voltage Reference Data 9.1.4. Device Configuration Information (DCI) 9.1.4.1. DIA and DCI Access 9.2. Data Memory Organization 9.2.1. Bank Selection 9.2.2. Core Registers 9.2.3. Special Function Register 9.2.4. General Purpose RAM 9.2.5. Common RAM 9.2.6. Device Memory Maps 9.3. STATUS Register 9.4. PCL and PCLATH 9.4.1. Modifying PCL 9.4.2. Computed GOTO 9.4.3. Computed Function Calls 9.4.4. Branching 9.5. Stack 9.5.1. Accessing the Stack 9.5.2. Overflow/Underflow Reset 9.6. Indirect Addressing 9.6.1. Traditional/Banked Data Memory 9.6.2. Linear Data Memory 9.6.3. Program Flash Memory 9.6.4. Data EEPROM Memory 9.7. Register Definitions: Memory Organization 9.7.1. INDF0 9.7.2. INDF1 9.7.3. PCL 9.7.4. STATUS 9.7.5. FSR0 9.7.6. FSR1 9.7.7. BSR 9.7.8. WREG 9.7.9. PCLATH 9.8. Register Summary - Memory Organization 10. Resets 10.1. Power-on Reset (POR) 10.1.1. Programming Mode Exit 10.2. Brown-out Reset (BOR) 10.2.1. BOR Is Always On 10.2.2. BOR Is Off in Sleep 10.2.3. BOR Controlled by Software 10.2.4. BOR Is Always Off 10.3. MCLR Reset 10.3.1. MCLR Enabled 10.3.2. MCLR Disabled 10.4. Watchdog Timer (WDT) Reset 10.5. RESET Instruction 10.6. Stack Overflow/Underflow Reset 10.7. Power-Up Timer (PWRT) 10.8. Start-Up Sequence 10.9. Memory Execution Violation 10.10. Determining the Cause of a Reset 10.11. Power Control (PCONx) Register 10.12. Register Definitions: Power Control 10.12.1. BORCON 10.12.2. PCON0 10.12.3. PCON1 10.13. Register Summary - Power Control 11. OSC - Oscillator Module 11.1. Clock Source Types 11.1.1. External Clock Sources 11.1.1.1. EC Mode 11.1.1.2. Secondary Oscillator 11.1.1.2.1. SOSC Start-Up Timing 11.1.2. Internal Clock Sources 11.1.2.1. HFINTOSC 11.1.2.1.1. HFINTOSC Frequency Tuning 11.1.2.2. MFINTOSC 11.1.2.3. SFINTOSC 11.1.2.4. LFINTOSC 11.1.2.5. ADCRC 11.1.3. Oscillator Status and Manual Enable 11.2. Active Clock Tuning (ACT) 11.2.1. ACT Lock Status 11.2.2. ACT Out-Of-Range Status 11.2.3. ACT Update Disable 11.2.4. ACT Interrupts 11.3. Register Definitions: Oscillator Module 11.3.1. ACTCON 11.3.2. OSCCON2 11.3.3. OSCCON3 11.3.4. OSCTUNE 11.3.5. OSCFRQ 11.3.6. OSCSTAT 11.3.7. OSCEN 11.4. Register Summary - Oscillator Module 12. INT - Interrupts 12.1. Overview 12.2. INTCON Register 12.3. PIE Registers 12.4. PIR Registers 12.5. Operation 12.6. Interrupt Latency 12.7. Interrupts During Sleep 12.8. INT Pin 12.9. Automatic Context Saving 12.10. Register Definitions: Interrupt Control 12.10.1. INTCON 12.10.2. PIE0 12.10.3. PIE1 12.10.4. PIE2 12.10.5. PIE3 12.10.6. PIE4 12.10.7. PIR0 12.10.8. PIR1 12.10.9. PIR2 12.10.10. PIR3 12.10.11. PIR4 12.11. Register Summary - Interrupt Control 13. Sleep Mode 13.1. Sleep Mode Operation 13.1.1. Wake-Up from Sleep 13.1.2. Wake-Up Using Interrupts 14. WDT - Watchdog Timer 14.1. Selectable Clock Sources 14.2. WDT Operating Modes 14.2.1. WDT Is Always On 14.2.2. WDT Is Off During Sleep 14.2.3. WDT Controlled by Software 14.2.4. WDT Is Off 14.3. WDT Time-Out Period 14.4. Clearing the WDT 14.5. WDT Operation During Sleep 14.6. Register Definitions: WDT Control 14.6.1. WDTCON 14.7. Register Summary - WDT Control 15. NVM - Nonvolatile Memory Control 15.1. Program Flash Memory (PFM) 15.1.1. FSR and INDF Access 15.1.1.1. FSR Read 15.1.1.2. FSR Write 15.1.2. NVMREG Access 15.1.2.1. NVMREG Read Operation 15.1.2.2. NVM Unlock Sequence 15.1.2.3. NVMREG Erase of Program Memory 15.1.2.4. NVMREG Write to Program Memory 15.1.2.5. Modifying Flash Program Memory 15.1.2.6. NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words 15.1.2.7. Write Verify 15.1.2.8. WRERR Bit 15.2. Data Flash Memory (DFM) 15.2.1. FSR and INDF Access 15.2.1.1. FSR DFM Read 15.2.1.2. FSR DFM Write 15.2.2. NVMREG Access 15.2.2.1. NVMREG Read Operation 15.2.2.2. NVM Unlock Sequence 15.2.2.3. NVMREG Erase of DFM 15.2.2.4. NVMREG Write to DFM 15.2.2.5. WRERR Bit 15.3. Register Definitions: Nonvolatile Memory Control 15.3.1. NVMADR 15.3.2. NVMDAT 15.3.3. NVMCON1 15.3.4. NVMCON2 15.4. Register Summary - NVM Control 16. I/O Ports 16.1. Overview 16.2. PORTx - Data Register 16.3. LATx - Output Latch 16.4. TRISx - Direction Control 16.5. ANSELx - Analog Control 16.6. WPUx - Weak Pull-Up Control 16.7. INLVLx - Input Threshold Control 16.8. SLRCONx - Slew Rate Control 16.9. ODCONx - Open-Drain Control 16.10. Edge Selectable Interrupt-on-Change 16.11. I2C Pad Control 16.12. I/O Priorities 16.13. MCLR/VPP/RE3 Pin 16.14. Register Definitions: Port Control 16.14.1. PORTx 16.14.2. LATx 16.14.3. TRISx 16.14.4. ANSELx 16.14.5. WPUx 16.14.6. INLVLx 16.14.7. SLRCONx 16.14.8. ODCONx 16.14.9. RxyI2C 16.15. Register Summary - IO Ports 17. IOC - Interrupt-on-Change 17.1. Overview 17.2. Enabling the Module 17.3. Individual Pin Configuration 17.4. Interrupt Flags 17.5. Clearing Interrupt Flags 17.6. Operation in Sleep 17.7. Register Definitions: Interrupt-on-Change Control 17.7.1. IOCxF 17.7.2. IOCxN 17.7.3. IOCxP 17.8. Register Summary - Interrupt-on-Change 18. PPS - Peripheral Pin Select Module 18.1. Overview 18.2. PPS Inputs 18.3. PPS Outputs 18.4. Bidirectional Pins 18.5. PPS Lock 18.5.1. PPS One-Way Lock 18.6. Operation During Sleep 18.7. Effects of a Reset 18.8. Register Definitions: Peripheral Pin Select (PPS) 18.8.1. xxxPPS 18.8.2. RxyPPS 18.8.3. PPSLOCK 18.9. Register Summary - Peripheral Pin Select Module 19. TMR0 - Timer0 Module 19.1. Timer0 Operation 19.1.1. 8-Bit Mode 19.1.2. 16-Bit Mode 19.2. Clock Selection 19.2.1. Synchronous Mode 19.2.2. Asynchronous Mode 19.2.3. Programmable Prescaler 19.2.4. Programmable Postscaler 19.3. Timer0 Output and Interrupt 19.3.1. Timer0 Output 19.3.2. Timer0 Interrupt 19.3.3. Timer0 Example 19.4. Operation During Sleep 19.5. Register Definitions: Timer0 Control 19.5.1. T0CON0 19.5.2. T0CON1 19.5.3. TMR0H 19.5.4. TMR0L 19.6. Register Summary - Timer0 20. TMR1 - Timer1 Module with Gate Control 20.1. Timer1 Operation 20.2. Clock Source Selection 20.2.1. Internal Clock Source 20.2.2. External Clock Source 20.3. Timer1 Prescaler 20.4. Secondary Oscillator 20.5. Timer1 Operation in Asynchronous Counter Mode 20.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 20.6. Timer1 16-Bit Read/Write Mode 20.7. Timer1 Gate 20.7.1. Timer1 Gate Enable 20.7.2. Timer1 Gate Source Selection 20.7.3. Timer1 Gate Toggle Mode 20.7.4. Timer1 Gate Single Pulse Mode 20.7.5. Timer1 Gate Value Status 20.7.6. Timer1 Gate Event Interrupt 20.8. Timer1 Interrupt 20.9. Timer1 Operation During Sleep 20.10. CCP Capture/Compare Time Base 20.11. CCP Special Event Trigger 20.12. Peripheral Module Disable 20.13. Register Definitions: Timer1 Control 20.13.1. TxCON 20.13.2. TxGCON 20.13.3. TxCLK 20.13.4. TxGATE 20.13.5. TMRx 20.14. Register Summary - Timer1 21. TMR2 - Timer2 Module 21.1. Timer2 Operation 21.1.1. Free-Running Period Mode 21.1.2. One Shot Mode 21.1.3. Monostable Mode 21.2. Timer2 Output 21.3. External Reset Sources 21.4. Timer2 Interrupt 21.5. PSYNC Bit 21.6. CSYNC Bit 21.7. Operating Modes 21.8. Operation Examples 21.8.1. Software Gate Mode 21.8.2. Hardware Gate Mode 21.8.3. Edge Triggered Hardware Limit Mode 21.8.4. Level Triggered Hardware Limit Mode 21.8.5. Software Start One Shot Mode 21.8.6. Edge Triggered One Shot Mode 21.8.7. Edge Triggered Hardware Limit One Shot Mode 21.8.8. Level Reset, Edge Triggered Hardware Limit One Shot Modes 21.8.9. Edge Triggered Monostable Modes 21.8.10. Level Triggered Hardware Limit One Shot Modes 21.9. Timer2 Operation During Sleep 21.10. Register Definitions: Timer2 Control 21.10.1. TxTMR 21.10.2. TxPR 21.10.3. TxCON 21.10.4. TxHLT 21.10.5. TxCLKCON 21.10.6. TxRST 21.11. Register Summary - Timer2 22. NCO - Numerically Controlled Oscillator Module 22.1. NCO Operation 22.1.1. NCO Clock Sources 22.1.2. Accumulator 22.1.3. Adder 22.1.4. Increment Registers 22.2. Fixed Duty Cycle Mode 22.3. Pulse Frequency Mode 22.4. Output Polarity Control 22.5. Interrupts 22.6. Effects of a Reset 22.7. Operation in Sleep 22.8. Register Definitions: NCO 22.8.1. NCOxCON 22.8.2. NCOxCLK 22.8.3. NCOxACC 22.8.4. NCOxINC 22.9. Register Summary - NCO 23. CWG - Complementary Waveform Generator Module 23.1. Fundamental Operation 23.2. Operating Modes 23.2.1. Half Bridge Mode 23.2.2. Push-Pull Mode 23.2.3. Full Bridge Mode 23.2.3.1. Direction Change in Full Bridge Mode 23.2.3.2. Dead-Band Delay in Full Bridge Mode 23.2.4. Steering Modes 23.2.4.1. Synchronous Steering Mode 23.2.4.2. Asynchronous Steering Mode 23.2.4.3. Start-Up Considerations 23.3. Clock Source 23.4. Selectable Input Sources 23.5. Output Control 23.5.1. CWG Output 23.5.2. Polarity Control 23.6. Dead-Band Control 23.6.1. Dead-Band Functionality in Half Bridge Mode 23.6.2. Dead-Band Functionality in Full Bridge Mode 23.7. Rising Edge and Reverse Dead Band 23.8. Falling Edge and Forward Dead Band 23.9. Dead-Band Jitter 23.10. Auto-Shutdown 23.10.1. Shutdown 23.10.2. Software Generated Shutdown 23.10.3. External Input Source 23.10.4. Pin Override Levels 23.10.5. Auto-Shutdown Interrupts 23.11. Auto-Shutdown Restart 23.11.1. Software-Controlled Restart 23.11.2. Auto-Restart 23.12. Operation During Sleep 23.13. Configuring the CWG 23.14. Register Definitions: CWG Control 23.14.1. CWGxCON0 23.14.2. CWGxCON1 23.14.3. CWGxCLK 23.14.4. CWGxISM 23.14.5. CWGxSTR 23.14.6. CWGxAS0 23.14.7. CWGxAS1 23.14.8. CWGxDBR 23.14.9. CWGxDBF 23.15. Register Summary - CWG 24. CCP - Capture/Compare/PWM Module 24.1. CCP Module Configuration 24.1.1. CCP Modules and Timer Resources 24.1.2. Open-Drain Output Option 24.2. Capture Mode 24.2.1. Capture Sources 24.2.2. Timer1 Mode for Capture 24.2.3. Software Interrupt Mode 24.2.4. CCP Prescaler 24.2.5. Capture During Sleep 24.3. Compare Mode 24.3.1. CCPx Pin Configuration 24.3.2. Timer1 Mode for Compare 24.3.3. Compare During Sleep 24.4. PWM Overview 24.4.1. Standard PWM Operation 24.4.2. Setup for PWM Operation 24.4.3. Timer2 Timer Resource 24.4.4. PWM Period 24.4.5. PWM Duty Cycle 24.4.6. PWM Resolution 24.4.7. Operation in Sleep Mode 24.4.8. Changes in System Clock Frequency 24.4.9. Effects of Reset 24.5. Register Definitions: CCP Control 24.5.1. CCPxCON 24.5.2. CCPxCAP 24.5.3. CCPRx 24.6. Register Summary - CCP Control 25. Capture, Compare, and PWM Timers Selection 25.1. Register Definitions: Capture, Compare, and PWM Timers Selection 25.1.1. CCPTMRS0 25.2. Register Summary - Capture, Compare, and PWM Timers Selection 26. PWM - Pulse-Width Modulation 26.1. Fundamental Operation 26.2. PWM Output Polarity 26.3. PWM Period 26.4. PWM Duty Cycle 26.5. PWM Resolution 26.6. Operation in Sleep Mode 26.7. Changes in System Clock Frequency 26.8. Effects of Reset 26.9. Setup for PWM Operation Using PWMx Output Pins 26.9.1. PWMx Pin Configuration 26.10. Setup for PWM Operation to Other Device Peripherals 26.11. Register Definitions: PWM Control 26.11.1. PWMxCON 26.11.2. PWMxDC 26.12. Register Summary - PWM 27. PWM Timers Selection 27.1. Register Definitions: Capture, Compare, and PWM Timers Selection 27.1.1. PWMTMRS0 27.2. Register Summary - Capture, Compare, and PWM Timers Selection 28. CLC - Configurable Logic Cell 28.1. CLC Setup 28.1.1. Data Selection 28.1.2. Data Gating 28.1.3. Logic Function 28.1.4. Output Polarity 28.2. CLC Interrupts 28.3. Effects of a Reset 28.4. Output Mirror Copies 28.5. Operation During Sleep 28.6. CLC Setup Steps 28.7. Register Overlay 28.8. Register Definitions: Configurable Logic Cell 28.8.1. CLCSELECT 28.8.2. CLCnCON 28.8.3. CLCnPOL 28.8.4. CLCnSEL0 28.8.5. CLCnSEL1 28.8.6. CLCnSEL2 28.8.7. CLCnSEL3 28.8.8. CLCnGLS0 28.8.9. CLCnGLS1 28.8.10. CLCnGLS2 28.8.11. CLCnGLS3 28.8.12. CLCDATA 28.9. Register Summary - CLC Control 29. MSSP - Host Synchronous Serial Port Module 29.1. SPI Mode Overview 29.1.1. SPI Mode Registers 29.1.2. SPI Mode Operation 29.1.2.1. SPI Host Mode 29.1.2.2. SPI Client Mode 29.1.2.3. Daisy-Chain Configuration 29.1.2.4. Client Select Synchronization 29.1.2.5. SPI Operation in Sleep Mode 29.2. I2C Mode Overview 29.2.1. I2C Mode Registers 29.2.2. I2C Mode Operation 29.2.2.1. Definition of I2C Terminology 29.2.2.2. Byte Format 29.2.2.3. SDA and SCL Pins 29.2.2.4. SDA Hold Time 29.2.2.5. Clock Stretching 29.2.2.6. Arbitration 29.2.2.7. Start Condition 29.2.2.8. Stop Condition 29.2.2.9. Start/Stop Condition Interrupt Masking 29.2.2.10. Restart Condition 29.2.2.11. Acknowledge Sequence 29.2.3. I2C Client Mode Operation 29.2.3.1. Client Mode Addresses 29.2.3.1.1. I2C Client 7-Bit Addressing Mode 29.2.3.1.2. I2C Client 10-Bit Addressing Mode 29.2.3.2. Clock Stretching 29.2.3.2.1. Normal Clock Stretching 29.2.3.2.2. 10-Bit Addressing Mode 29.2.3.2.3. Byte NACKing 29.2.3.3. Clock Synchronization and the CKP Bit 29.2.3.4. General Call Address Support 29.2.3.5. SSP Mask Register 29.2.3.6. Client Reception 29.2.3.6.1. 7-Bit Addressing Reception 29.2.3.6.2. 7-Bit Reception with AHEN and DHEN 29.2.3.6.3. Client Mode 10-Bit Address Reception 29.2.3.6.4. 10-Bit Addressing with Address or Data Hold 29.2.3.7. Client Transmission 29.2.3.7.1. Client Mode Bus Collision 29.2.3.7.2. 7-Bit Transmission 29.2.3.7.3. 7-Bit Transmission with Address Hold Enabled 29.2.4. I2C Host Mode 29.2.4.1. I2C Host Mode Operation 29.2.4.1.1. Clock Arbitration 29.2.4.1.2. WCOL Status Flag 29.2.4.1.3. I2C Host Mode Start Condition Timing 29.2.4.1.4. I2C Host Mode Repeated Start Condition Timing 29.2.4.1.5. Acknowledge Sequence Timing 29.2.4.1.5.1. Acknowledge Write Collision 29.2.4.1.6. Stop Condition Timing 29.2.4.1.6.1. Write Collision on Stop 29.2.4.1.7. Sleep Operation 29.2.4.1.8. Effects of a Reset 29.2.4.2. I2C Host Mode Transmission 29.2.4.2.1. BF Status Flag 29.2.4.2.2. WCOL Status Flag 29.2.4.2.3. ACKSTAT Status Flag 29.2.4.2.4. Typical Transmit Sequence 29.2.4.3. I2C Host Mode Reception 29.2.4.3.1. BF Status Flag 29.2.4.3.2. SSPOV Status Flag 29.2.4.3.3. WCOL Status Flag 29.2.4.3.4. Typical Receive Sequence 29.2.5. Multi-Host Mode 29.2.5.1. Multi-Host Communication, Bus Collision and Bus Arbitration 29.2.5.1.1. Bus Collision During a Start Condition 29.2.5.1.2. Bus Collision During a Repeated Start Condition 29.2.5.1.3. Bus Collision During a Stop Condition 29.3. Baud Rate Generator 29.4. Register Definitions: MSSP Control 29.4.1. SSPxBUF 29.4.2. SSPxADD 29.4.3. SSPxMSK 29.4.4. SSPxSTAT 29.4.5. SSPxCON1 29.4.6. SSPxCON2 29.4.7. SSPxCON3 29.5. Register Summary - MSSP Control 30. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 30.1. EUSART Asynchronous Mode 30.1.1. EUSART Asynchronous Transmitter 30.1.1.1. Enabling the Transmitter 30.1.1.2. Transmitting Data 30.1.1.3. Transmit Data Polarity 30.1.1.4. Transmit Interrupt Flag 30.1.1.5. TSR Status 30.1.1.6. Transmitting 9-Bit Characters 30.1.1.7. Asynchronous Transmission Setup 30.1.2. EUSART Asynchronous Receiver 30.1.2.1. Enabling the Receiver 30.1.2.2. Receiving Data 30.1.2.3. Receive Interrupts 30.1.2.4. Receive Framing Error 30.1.2.5. Receive Overrun Error 30.1.2.6. Receiving 9-Bit Characters 30.1.2.7. Address Detection 30.1.2.8. Asynchronous Reception Setup 30.1.2.9. 9-Bit Address Detection Mode Setup 30.2. Clock Accuracy with Asynchronous Operation 30.3. EUSART Baud Rate Generator (BRG) 30.3.1. Auto-Baud Detect 30.3.2. Auto-Baud Overflow 30.3.3. Auto-Wake-Up on Break 30.3.3.1. Special Considerations 30.3.4. Break Character Sequence 30.3.4.1. Break and Sync Transmit Sequence 30.3.5. Receiving a Break Character 30.4. EUSART Synchronous Mode 30.4.1. Synchronous Host Mode 30.4.1.1. Host Clock 30.4.1.2. Clock Polarity 30.4.1.3. Synchronous Host Transmission 30.4.1.4. Synchronous Host Transmission Setup 30.4.1.5. Synchronous Host Reception 30.4.1.6. Client Clock 30.4.1.7. Receive Overrun Error 30.4.1.8. Receiving 9-Bit Characters 30.4.1.9. Synchronous Host Reception Setup 30.4.2. Synchronous Client Mode 30.4.2.1. EUSART Synchronous Client Transmit 30.4.2.2. Synchronous Client Transmission Setup 30.4.2.3. EUSART Synchronous Client Reception 30.4.2.4. Synchronous Client Reception Setup 30.5. EUSART Operation During Sleep 30.5.1. Synchronous Receive During Sleep 30.5.2. Synchronous Transmit During Sleep 30.6. Register Definitions: EUSART Control 30.6.1. TXxSTA 30.6.2. RCxSTA 30.6.3. BAUDxCON 30.6.4. RCxREG 30.6.5. TXxREG 30.6.6. SPxBRG 30.7. Register Summary - EUSART 31. ADC - Analog-to-Digital Converter with Computation Module 31.1. ADC Configuration 31.1.1. Port Configuration 31.1.2. Channel Selection 31.1.2.1. Channel Grouping 31.1.3. ADC Voltage Reference 31.1.4. Conversion Clock 31.1.5. Interrupts 31.1.6. Result Formatting 31.2. ADC Operation 31.2.1. Starting a Conversion 31.2.2. Completion of a Conversion 31.2.3. ADC Operation During Sleep 31.2.4. External Trigger During Sleep 31.2.5. Auto-Conversion Trigger 31.2.6. ADC Conversion Procedure (Basic Mode) 31.3. ADC Acquisition Requirements 31.4. Computation Operation 31.4.1. Digital Filter/Average 31.4.2. Basic Mode 31.4.3. Accumulate Mode 31.4.4. Average Mode 31.4.5. Burst Average Mode 31.4.6. Low-Pass Filter Mode 31.4.7. Threshold Comparison 31.4.8. Repetition and Sampling Options 31.4.8.1. Continuous Sampling Mode 31.4.8.2. Double Sample Conversion 31.4.9. Capacitive Voltage Divider (CVD) Features 31.4.9.1. CVD Operation 31.4.9.2. Precharge Control 31.4.9.3. Acquisition Control for CVD (ADPRE > 0) 31.4.9.4. Guard Ring Outputs 31.4.9.5. Additional Sample-and-Hold Capacitance 31.5. Register Definitions: ADC Control 31.5.1. ADCON0 31.5.2. ADCON1 31.5.3. ADCON2 31.5.4. ADCON3 31.5.5. ADSTAT 31.5.6. ADCLK 31.5.7. ADREF 31.5.8. ADPCH 31.5.9. ADPRE 31.5.10. ADACQ 31.5.11. ADCAP 31.5.12. ADRPT 31.5.13. ADCNT 31.5.14. ADFLTR 31.5.15. ADRES 31.5.16. ADPREV 31.5.17. ADACC 31.5.18. ADSTPT 31.5.19. ADERR 31.5.20. ADLTH 31.5.21. ADUTH 31.5.22. ADACT 31.5.23. ADCGxA 31.5.24. ADCGxB 31.5.25. ADCGxC 31.5.26. ADCGxD 31.5.27. ADCGxE 31.6. Register Summary - ADC 32. DAC - Digital-to-Analog Converter Module 32.1. Output Voltage Selection 32.2. Ratiometric Output Level 32.3. Buffered DAC Output Range Selection 32.4. Operation During Sleep 32.5. Effects of a Reset 32.6. Register Definitions: DAC Control 32.6.1. DACxCON 32.6.2. DACxDATL 32.7. Register Summary - DAC 33. CMP - Comparator Module 33.1. Comparator Overview 33.2. Comparator Control 33.2.1. Comparator Enable 33.2.2. Comparator Output 33.2.3. Comparator Output Polarity 33.3. Comparator Output Synchronization 33.4. Comparator Hysteresis 33.5. Comparator Interrupt 33.6. Comparator Positive Input Selection 33.7. Comparator Negative Input Selection 33.8. Comparator Response Time 33.9. Analog Input Connection Considerations 33.10. Operation in Sleep Mode 33.11. ADC Auto-Trigger Source 33.12. Register Definitions: Comparator Control 33.12.1. CMxCON0 33.12.2. CMxCON1 33.12.3. CMxNCH 33.12.4. CMxPCH 33.12.5. CMOUT 33.13. Register Summary - Comparator 34. FVR - Fixed Voltage Reference 34.1. Independent Gain Amplifiers 34.2. FVR Stabilization Period 34.3. Register Definitions: FVR 34.3.1. FVRCON 34.4. Register Summary - FVR 35. Temperature Indicator Module 35.1. Module Operation 35.1.1. Temperature Indicator Range 35.1.2. Minimum Operating VDD 35.2. Temperature Calculation 35.3. ADC Acquisition Time 35.4. Register Definitions: Temperature Indicator 35.4.1. FVRCON 35.5. Register Summary - Temperature Indicator 36. ZCD - Zero-Cross Detection Module 36.1. External Resistor Selection 36.2. ZCD Logic Output 36.3. ZCD Logic Polarity 36.4. ZCD Interrupts 36.5. Correction for ZCPINV Offset 36.5.1. Correction by AC Coupling 36.5.2. Correction by Offset Current 36.6. Handling VPEAK Variations 36.7. Operation During Sleep 36.8. Effects of a Reset 36.9. Disabling the ZCD Module 36.10. Register Definitions: ZCD Control 36.10.1. ZCDCON 36.11. Register Summary - ZCD 37. Charge Pump 37.1. Manually Enabled 37.2. Automatically Enabled 37.3. Disabled 37.4. Charge Pump Oscillator 37.5. Charge Pump Threshold 37.6. Charge Pump Ready 37.7. Register Definitions: Charge Pump 37.7.1. CPCON 37.8. Register Summary - Charge Pump 38. Instruction Set Summary 38.1. Read-Modify-Write Operations 38.2. Standard Instruction Set 38.2.1. Standard Instruction Set 39. ICSP™ - In-Circuit Serial Programming™ 39.1. High-Voltage Programming Entry Mode 39.2. Low-Voltage Programming Entry Mode 39.3. Common Programming Interfaces 40. Register Summary 41. Electrical Specifications 41.1. Absolute Maximum Ratings(†) 41.2. Standard Operating Conditions 41.3. DC Characteristics 41.3.1. Supply Voltage 41.3.2. Supply Current (IDD)(1,2) 41.3.3. Power-Down Current (IPD)(1,2,3) 41.3.4. I/O Ports 41.3.5. Memory Programming Specifications 41.3.6. Thermal Characteristics 41.4. AC Characteristics 41.4.1. External Clock/Oscillator Timing Requirements 41.4.2. Internal Oscillator Parameters(1) 41.4.3. I/O and CLKOUT Timing Specifications 41.4.4. Timer0 and Timer1 External Clock Requirements 41.4.5. Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications 41.4.6. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 41.4.7. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 41.4.8. 8-Bit DAC Specifications 41.4.9. Comparator Specifications 41.4.10. Zero-Cross Detect (ZCD) Specifications 41.4.11. Fixed Voltage Reference (FVR) Specifications 41.4.12. Temperature Indicator Requirements 41.4.13. Capture/Compare/PWM Requirements (CCP) 41.4.14. EUSART Synchronous Transmission Requirements 41.4.15. EUSART Synchronous Receive Requirements 41.4.16. SPI Mode Requirements 41.4.17. I2C Bus Start/Stop Bits Requirements 41.4.18. I2C Bus Data Requirements 41.4.19. Configurable Logic Cell (CLC) Characteristics 42. DC and AC Characteristics Graphs and Tables 43. Packaging Information 43.1. Package Details 44. Appendix A: Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
• One Configurable 8/16-Bit Timer (TMR0) • Two 16-Bit Timers (TMR1/3) with Gate Control • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) • One Numerically Controlled Oscillator (NCO): – Generates true linear frequency control and increased frequency resolution – Input clock up to 64 MHz • Up to Two Enhanced Universal Synchronous Asynchronous Receiver Transmitters (EUSART): – RS-232, RS-485, and LIN compatible – Auto wake-up on Start • Up to Two Host Synchronous Serial Ports (MSSP): – Serial Peripheral Interface (SPI) mode: • Client select synchronization – Inter-Integrated Circuit (I2C) mode: • 7/10-bit Addressing modes • Peripheral Pin Select (PPS): – Enables pin mapping of digital I/O • Device I/O Port Features: – Up to 35 I/O pins – One input-only pin – Individual I/O direction, open-drain, input threshold, slew rate, and weak pull-up control – Interrupt-on-Change (IOC) on up to 25 pins – One external interrupt pin
Analog Peripherals
• Analog-to-Digital Converter with Computation (ADCC): – 10-bit resolution – Up to 35 external input channels – Four internal input channels – Internal ADC oscillator (ADCRC) – Operates in Sleep – Selectable auto-conversion trigger sources • Charge Pump Module: – Improves accuracy of analog modules at low voltages • 8-Bit Digital-to-Analog Converter (DAC): – Output available on one I/O pin – Internal connections to ADC and Comparators • One Comparator (CMP): – Up to four external inputs – Configurable output polarity – External output via Peripheral Pin Select • Zero-Cross Detect (ZCD): – Detect when AC signal on pin crosses ground • Two Fixed Voltage References (FVR): – Selectable 1.024V, 2.048V, and 4.096V output levels – FVR1 internally connected to ADC – FVR2 internally connected to Comparator © 2021-2022 Microchip Technology Inc.
Preliminary Datasheet
DS40002325B-page 4 and its subsidiaries Document Outline Introduction PIC16F180 Family Summary Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Block Diagram Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables 4. Guidelines for Getting Started with PIC16F180 Microcontrollers 4.1. Basic Connection Requirements 4.2. Power Supply Pins 4.2.1. Decoupling Capacitors 4.2.2. Tank Capacitors 4.3. Master Clear (MCLR) Pin 4.4. In-Circuit Serial Programming™ (ICSP™) Pins 4.5. Unused I/Os 5. Register and Bit Naming Conventions 5.1. Register Names 5.2. Bit Names 5.2.1. Short Bit Names 5.2.2. Long Bit Names 5.2.3. Bit Fields 5.3. Register and Bit Naming Exceptions 5.3.1. Status, Interrupt and Mirror Bits 6. Register Legend 7. Enhanced Mid-Range CPU 7.1. Automatic Interrupt Context Saving 7.2. 16-Level Stack with Overflow and Underflow 7.3. File Select Registers 7.4. Instruction Set 8. Device Configuration 8.1. Configuration Words 8.2. Code Protection 8.3. Write Protection 8.4. User ID 8.5. Device ID and Revision ID 8.6. Register Definitions: Configuration Settings 8.6.1. CONFIG1 8.6.2. CONFIG2 8.6.3. CONFIG3 8.6.4. CONFIG4 8.6.5. CONFIG5 8.7. Register Definitions: Device ID and Revision ID 8.7.1. Device ID 8.7.2. Revision ID 9. Memory Organization 9.1. Program Memory Organization 9.1.1. Reading Program Memory as Data 9.1.1.1. RETLW Instruction 9.1.1.2. Indirect Read with FSR 9.1.2. Memory Access Partition (MAP) 9.1.2.1. Application Block 9.1.2.2. Boot Block 9.1.2.3. Storage Area Flash 9.1.2.4. Memory Write Protection 9.1.2.5. Memory Violation 9.1.3. Device Information Area (DIA) 9.1.3.1. Microchip Unique Identifier (MUI) 9.1.3.2. External Unique Identifier (EUI) 9.1.3.3. Standard Parameters for the Temperature Sensor 9.1.3.4. Fixed Voltage Reference Data 9.1.4. Device Configuration Information (DCI) 9.1.4.1. DIA and DCI Access 9.2. Data Memory Organization 9.2.1. Bank Selection 9.2.2. Core Registers 9.2.3. Special Function Register 9.2.4. General Purpose RAM 9.2.5. Common RAM 9.2.6. Device Memory Maps 9.3. STATUS Register 9.4. PCL and PCLATH 9.4.1. Modifying PCL 9.4.2. Computed GOTO 9.4.3. Computed Function Calls 9.4.4. Branching 9.5. Stack 9.5.1. Accessing the Stack 9.5.2. Overflow/Underflow Reset 9.6. Indirect Addressing 9.6.1. Traditional/Banked Data Memory 9.6.2. Linear Data Memory 9.6.3. Program Flash Memory 9.6.4. Data EEPROM Memory 9.7. Register Definitions: Memory Organization 9.7.1. INDF0 9.7.2. INDF1 9.7.3. PCL 9.7.4. STATUS 9.7.5. FSR0 9.7.6. FSR1 9.7.7. BSR 9.7.8. WREG 9.7.9. PCLATH 9.8. Register Summary - Memory Organization 10. Resets 10.1. Power-on Reset (POR) 10.1.1. Programming Mode Exit 10.2. Brown-out Reset (BOR) 10.2.1. BOR Is Always On 10.2.2. BOR Is Off in Sleep 10.2.3. BOR Controlled by Software 10.2.4. BOR Is Always Off 10.3. MCLR Reset 10.3.1. MCLR Enabled 10.3.2. MCLR Disabled 10.4. Watchdog Timer (WDT) Reset 10.5. RESET Instruction 10.6. Stack Overflow/Underflow Reset 10.7. Power-Up Timer (PWRT) 10.8. Start-Up Sequence 10.9. Memory Execution Violation 10.10. Determining the Cause of a Reset 10.11. Power Control (PCONx) Register 10.12. Register Definitions: Power Control 10.12.1. BORCON 10.12.2. PCON0 10.12.3. PCON1 10.13. Register Summary - Power Control 11. OSC - Oscillator Module 11.1. Clock Source Types 11.1.1. External Clock Sources 11.1.1.1. EC Mode 11.1.1.2. Secondary Oscillator 11.1.1.2.1. SOSC Start-Up Timing 11.1.2. Internal Clock Sources 11.1.2.1. HFINTOSC 11.1.2.1.1. HFINTOSC Frequency Tuning 11.1.2.2. MFINTOSC 11.1.2.3. SFINTOSC 11.1.2.4. LFINTOSC 11.1.2.5. ADCRC 11.1.3. Oscillator Status and Manual Enable 11.2. Active Clock Tuning (ACT) 11.2.1. ACT Lock Status 11.2.2. ACT Out-Of-Range Status 11.2.3. ACT Update Disable 11.2.4. ACT Interrupts 11.3. Register Definitions: Oscillator Module 11.3.1. ACTCON 11.3.2. OSCCON2 11.3.3. OSCCON3 11.3.4. OSCTUNE 11.3.5. OSCFRQ 11.3.6. OSCSTAT 11.3.7. OSCEN 11.4. Register Summary - Oscillator Module 12. INT - Interrupts 12.1. Overview 12.2. INTCON Register 12.3. PIE Registers 12.4. PIR Registers 12.5. Operation 12.6. Interrupt Latency 12.7. Interrupts During Sleep 12.8. INT Pin 12.9. Automatic Context Saving 12.10. Register Definitions: Interrupt Control 12.10.1. INTCON 12.10.2. PIE0 12.10.3. PIE1 12.10.4. PIE2 12.10.5. PIE3 12.10.6. PIE4 12.10.7. PIR0 12.10.8. PIR1 12.10.9. PIR2 12.10.10. PIR3 12.10.11. PIR4 12.11. Register Summary - Interrupt Control 13. Sleep Mode 13.1. Sleep Mode Operation 13.1.1. Wake-Up from Sleep 13.1.2. Wake-Up Using Interrupts 14. WDT - Watchdog Timer 14.1. Selectable Clock Sources 14.2. WDT Operating Modes 14.2.1. WDT Is Always On 14.2.2. WDT Is Off During Sleep 14.2.3. WDT Controlled by Software 14.2.4. WDT Is Off 14.3. WDT Time-Out Period 14.4. Clearing the WDT 14.5. WDT Operation During Sleep 14.6. Register Definitions: WDT Control 14.6.1. WDTCON 14.7. Register Summary - WDT Control 15. NVM - Nonvolatile Memory Control 15.1. Program Flash Memory (PFM) 15.1.1. FSR and INDF Access 15.1.1.1. FSR Read 15.1.1.2. FSR Write 15.1.2. NVMREG Access 15.1.2.1. NVMREG Read Operation 15.1.2.2. NVM Unlock Sequence 15.1.2.3. NVMREG Erase of Program Memory 15.1.2.4. NVMREG Write to Program Memory 15.1.2.5. Modifying Flash Program Memory 15.1.2.6. NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words 15.1.2.7. Write Verify 15.1.2.8. WRERR Bit 15.2. Data Flash Memory (DFM) 15.2.1. FSR and INDF Access 15.2.1.1. FSR DFM Read 15.2.1.2. FSR DFM Write 15.2.2. NVMREG Access 15.2.2.1. NVMREG Read Operation 15.2.2.2. NVM Unlock Sequence 15.2.2.3. NVMREG Erase of DFM 15.2.2.4. NVMREG Write to DFM 15.2.2.5. WRERR Bit 15.3. Register Definitions: Nonvolatile Memory Control 15.3.1. NVMADR 15.3.2. NVMDAT 15.3.3. NVMCON1 15.3.4. NVMCON2 15.4. Register Summary - NVM Control 16. I/O Ports 16.1. Overview 16.2. PORTx - Data Register 16.3. LATx - Output Latch 16.4. TRISx - Direction Control 16.5. ANSELx - Analog Control 16.6. WPUx - Weak Pull-Up Control 16.7. INLVLx - Input Threshold Control 16.8. SLRCONx - Slew Rate Control 16.9. ODCONx - Open-Drain Control 16.10. Edge Selectable Interrupt-on-Change 16.11. I2C Pad Control 16.12. I/O Priorities 16.13. MCLR/VPP/RE3 Pin 16.14. Register Definitions: Port Control 16.14.1. PORTx 16.14.2. LATx 16.14.3. TRISx 16.14.4. ANSELx 16.14.5. WPUx 16.14.6. INLVLx 16.14.7. SLRCONx 16.14.8. ODCONx 16.14.9. RxyI2C 16.15. Register Summary - IO Ports 17. IOC - Interrupt-on-Change 17.1. Overview 17.2. Enabling the Module 17.3. Individual Pin Configuration 17.4. Interrupt Flags 17.5. Clearing Interrupt Flags 17.6. Operation in Sleep 17.7. Register Definitions: Interrupt-on-Change Control 17.7.1. IOCxF 17.7.2. IOCxN 17.7.3. IOCxP 17.8. Register Summary - Interrupt-on-Change 18. PPS - Peripheral Pin Select Module 18.1. Overview 18.2. PPS Inputs 18.3. PPS Outputs 18.4. Bidirectional Pins 18.5. PPS Lock 18.5.1. PPS One-Way Lock 18.6. Operation During Sleep 18.7. Effects of a Reset 18.8. Register Definitions: Peripheral Pin Select (PPS) 18.8.1. xxxPPS 18.8.2. RxyPPS 18.8.3. PPSLOCK 18.9. Register Summary - Peripheral Pin Select Module 19. TMR0 - Timer0 Module 19.1. Timer0 Operation 19.1.1. 8-Bit Mode 19.1.2. 16-Bit Mode 19.2. Clock Selection 19.2.1. Synchronous Mode 19.2.2. Asynchronous Mode 19.2.3. Programmable Prescaler 19.2.4. Programmable Postscaler 19.3. Timer0 Output and Interrupt 19.3.1. Timer0 Output 19.3.2. Timer0 Interrupt 19.3.3. Timer0 Example 19.4. Operation During Sleep 19.5. Register Definitions: Timer0 Control 19.5.1. T0CON0 19.5.2. T0CON1 19.5.3. TMR0H 19.5.4. TMR0L 19.6. Register Summary - Timer0 20. TMR1 - Timer1 Module with Gate Control 20.1. Timer1 Operation 20.2. Clock Source Selection 20.2.1. Internal Clock Source 20.2.2. External Clock Source 20.3. Timer1 Prescaler 20.4. Secondary Oscillator 20.5. Timer1 Operation in Asynchronous Counter Mode 20.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 20.6. Timer1 16-Bit Read/Write Mode 20.7. Timer1 Gate 20.7.1. Timer1 Gate Enable 20.7.2. Timer1 Gate Source Selection 20.7.3. Timer1 Gate Toggle Mode 20.7.4. Timer1 Gate Single Pulse Mode 20.7.5. Timer1 Gate Value Status 20.7.6. Timer1 Gate Event Interrupt 20.8. Timer1 Interrupt 20.9. Timer1 Operation During Sleep 20.10. CCP Capture/Compare Time Base 20.11. CCP Special Event Trigger 20.12. Peripheral Module Disable 20.13. Register Definitions: Timer1 Control 20.13.1. TxCON 20.13.2. TxGCON 20.13.3. TxCLK 20.13.4. TxGATE 20.13.5. TMRx 20.14. Register Summary - Timer1 21. TMR2 - Timer2 Module 21.1. Timer2 Operation 21.1.1. Free-Running Period Mode 21.1.2. One Shot Mode 21.1.3. Monostable Mode 21.2. Timer2 Output 21.3. External Reset Sources 21.4. Timer2 Interrupt 21.5. PSYNC Bit 21.6. CSYNC Bit 21.7. Operating Modes 21.8. Operation Examples 21.8.1. Software Gate Mode 21.8.2. Hardware Gate Mode 21.8.3. Edge Triggered Hardware Limit Mode 21.8.4. Level Triggered Hardware Limit Mode 21.8.5. Software Start One Shot Mode 21.8.6. Edge Triggered One Shot Mode 21.8.7. Edge Triggered Hardware Limit One Shot Mode 21.8.8. Level Reset, Edge Triggered Hardware Limit One Shot Modes 21.8.9. Edge Triggered Monostable Modes 21.8.10. Level Triggered Hardware Limit One Shot Modes 21.9. Timer2 Operation During Sleep 21.10. Register Definitions: Timer2 Control 21.10.1. TxTMR 21.10.2. TxPR 21.10.3. TxCON 21.10.4. TxHLT 21.10.5. TxCLKCON 21.10.6. TxRST 21.11. Register Summary - Timer2 22. NCO - Numerically Controlled Oscillator Module 22.1. NCO Operation 22.1.1. NCO Clock Sources 22.1.2. Accumulator 22.1.3. Adder 22.1.4. Increment Registers 22.2. Fixed Duty Cycle Mode 22.3. Pulse Frequency Mode 22.4. Output Polarity Control 22.5. Interrupts 22.6. Effects of a Reset 22.7. Operation in Sleep 22.8. Register Definitions: NCO 22.8.1. NCOxCON 22.8.2. NCOxCLK 22.8.3. NCOxACC 22.8.4. NCOxINC 22.9. Register Summary - NCO 23. CWG - Complementary Waveform Generator Module 23.1. Fundamental Operation 23.2. Operating Modes 23.2.1. Half Bridge Mode 23.2.2. Push-Pull Mode 23.2.3. Full Bridge Mode 23.2.3.1. Direction Change in Full Bridge Mode 23.2.3.2. Dead-Band Delay in Full Bridge Mode 23.2.4. Steering Modes 23.2.4.1. Synchronous Steering Mode 23.2.4.2. Asynchronous Steering Mode 23.2.4.3. Start-Up Considerations 23.3. Clock Source 23.4. Selectable Input Sources 23.5. Output Control 23.5.1. CWG Output 23.5.2. Polarity Control 23.6. Dead-Band Control 23.6.1. Dead-Band Functionality in Half Bridge Mode 23.6.2. Dead-Band Functionality in Full Bridge Mode 23.7. Rising Edge and Reverse Dead Band 23.8. Falling Edge and Forward Dead Band 23.9. Dead-Band Jitter 23.10. Auto-Shutdown 23.10.1. Shutdown 23.10.2. Software Generated Shutdown 23.10.3. External Input Source 23.10.4. Pin Override Levels 23.10.5. Auto-Shutdown Interrupts 23.11. Auto-Shutdown Restart 23.11.1. Software-Controlled Restart 23.11.2. Auto-Restart 23.12. Operation During Sleep 23.13. Configuring the CWG 23.14. Register Definitions: CWG Control 23.14.1. CWGxCON0 23.14.2. CWGxCON1 23.14.3. CWGxCLK 23.14.4. CWGxISM 23.14.5. CWGxSTR 23.14.6. CWGxAS0 23.14.7. CWGxAS1 23.14.8. CWGxDBR 23.14.9. CWGxDBF 23.15. Register Summary - CWG 24. CCP - Capture/Compare/PWM Module 24.1. CCP Module Configuration 24.1.1. CCP Modules and Timer Resources 24.1.2. Open-Drain Output Option 24.2. Capture Mode 24.2.1. Capture Sources 24.2.2. Timer1 Mode for Capture 24.2.3. Software Interrupt Mode 24.2.4. CCP Prescaler 24.2.5. Capture During Sleep 24.3. Compare Mode 24.3.1. CCPx Pin Configuration 24.3.2. Timer1 Mode for Compare 24.3.3. Compare During Sleep 24.4. PWM Overview 24.4.1. Standard PWM Operation 24.4.2. Setup for PWM Operation 24.4.3. Timer2 Timer Resource 24.4.4. PWM Period 24.4.5. PWM Duty Cycle 24.4.6. PWM Resolution 24.4.7. Operation in Sleep Mode 24.4.8. Changes in System Clock Frequency 24.4.9. Effects of Reset 24.5. Register Definitions: CCP Control 24.5.1. CCPxCON 24.5.2. CCPxCAP 24.5.3. CCPRx 24.6. Register Summary - CCP Control 25. Capture, Compare, and PWM Timers Selection 25.1. Register Definitions: Capture, Compare, and PWM Timers Selection 25.1.1. CCPTMRS0 25.2. Register Summary - Capture, Compare, and PWM Timers Selection 26. PWM - Pulse-Width Modulation 26.1. Fundamental Operation 26.2. PWM Output Polarity 26.3. PWM Period 26.4. PWM Duty Cycle 26.5. PWM Resolution 26.6. Operation in Sleep Mode 26.7. Changes in System Clock Frequency 26.8. Effects of Reset 26.9. Setup for PWM Operation Using PWMx Output Pins 26.9.1. PWMx Pin Configuration 26.10. Setup for PWM Operation to Other Device Peripherals 26.11. Register Definitions: PWM Control 26.11.1. PWMxCON 26.11.2. PWMxDC 26.12. Register Summary - PWM 27. PWM Timers Selection 27.1. Register Definitions: Capture, Compare, and PWM Timers Selection 27.1.1. PWMTMRS0 27.2. Register Summary - Capture, Compare, and PWM Timers Selection 28. CLC - Configurable Logic Cell 28.1. CLC Setup 28.1.1. Data Selection 28.1.2. Data Gating 28.1.3. Logic Function 28.1.4. Output Polarity 28.2. CLC Interrupts 28.3. Effects of a Reset 28.4. Output Mirror Copies 28.5. Operation During Sleep 28.6. CLC Setup Steps 28.7. Register Overlay 28.8. Register Definitions: Configurable Logic Cell 28.8.1. CLCSELECT 28.8.2. CLCnCON 28.8.3. CLCnPOL 28.8.4. CLCnSEL0 28.8.5. CLCnSEL1 28.8.6. CLCnSEL2 28.8.7. CLCnSEL3 28.8.8. CLCnGLS0 28.8.9. CLCnGLS1 28.8.10. CLCnGLS2 28.8.11. CLCnGLS3 28.8.12. CLCDATA 28.9. Register Summary - CLC Control 29. MSSP - Host Synchronous Serial Port Module 29.1. SPI Mode Overview 29.1.1. SPI Mode Registers 29.1.2. SPI Mode Operation 29.1.2.1. SPI Host Mode 29.1.2.2. SPI Client Mode 29.1.2.3. Daisy-Chain Configuration 29.1.2.4. Client Select Synchronization 29.1.2.5. SPI Operation in Sleep Mode 29.2. I2C Mode Overview 29.2.1. I2C Mode Registers 29.2.2. I2C Mode Operation 29.2.2.1. Definition of I2C Terminology 29.2.2.2. Byte Format 29.2.2.3. SDA and SCL Pins 29.2.2.4. SDA Hold Time 29.2.2.5. Clock Stretching 29.2.2.6. Arbitration 29.2.2.7. Start Condition 29.2.2.8. Stop Condition 29.2.2.9. Start/Stop Condition Interrupt Masking 29.2.2.10. Restart Condition 29.2.2.11. Acknowledge Sequence 29.2.3. I2C Client Mode Operation 29.2.3.1. Client Mode Addresses 29.2.3.1.1. I2C Client 7-Bit Addressing Mode 29.2.3.1.2. I2C Client 10-Bit Addressing Mode 29.2.3.2. Clock Stretching 29.2.3.2.1. Normal Clock Stretching 29.2.3.2.2. 10-Bit Addressing Mode 29.2.3.2.3. Byte NACKing 29.2.3.3. Clock Synchronization and the CKP Bit 29.2.3.4. General Call Address Support 29.2.3.5. SSP Mask Register 29.2.3.6. Client Reception 29.2.3.6.1. 7-Bit Addressing Reception 29.2.3.6.2. 7-Bit Reception with AHEN and DHEN 29.2.3.6.3. Client Mode 10-Bit Address Reception 29.2.3.6.4. 10-Bit Addressing with Address or Data Hold 29.2.3.7. Client Transmission 29.2.3.7.1. Client Mode Bus Collision 29.2.3.7.2. 7-Bit Transmission 29.2.3.7.3. 7-Bit Transmission with Address Hold Enabled 29.2.4. I2C Host Mode 29.2.4.1. I2C Host Mode Operation 29.2.4.1.1. Clock Arbitration 29.2.4.1.2. WCOL Status Flag 29.2.4.1.3. I2C Host Mode Start Condition Timing 29.2.4.1.4. I2C Host Mode Repeated Start Condition Timing 29.2.4.1.5. Acknowledge Sequence Timing 29.2.4.1.5.1. Acknowledge Write Collision 29.2.4.1.6. Stop Condition Timing 29.2.4.1.6.1. Write Collision on Stop 29.2.4.1.7. Sleep Operation 29.2.4.1.8. Effects of a Reset 29.2.4.2. I2C Host Mode Transmission 29.2.4.2.1. BF Status Flag 29.2.4.2.2. WCOL Status Flag 29.2.4.2.3. ACKSTAT Status Flag 29.2.4.2.4. Typical Transmit Sequence 29.2.4.3. I2C Host Mode Reception 29.2.4.3.1. BF Status Flag 29.2.4.3.2. SSPOV Status Flag 29.2.4.3.3. WCOL Status Flag 29.2.4.3.4. Typical Receive Sequence 29.2.5. Multi-Host Mode 29.2.5.1. Multi-Host Communication, Bus Collision and Bus Arbitration 29.2.5.1.1. Bus Collision During a Start Condition 29.2.5.1.2. Bus Collision During a Repeated Start Condition 29.2.5.1.3. Bus Collision During a Stop Condition 29.3. Baud Rate Generator 29.4. Register Definitions: MSSP Control 29.4.1. SSPxBUF 29.4.2. SSPxADD 29.4.3. SSPxMSK 29.4.4. SSPxSTAT 29.4.5. SSPxCON1 29.4.6. SSPxCON2 29.4.7. SSPxCON3 29.5. Register Summary - MSSP Control 30. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 30.1. EUSART Asynchronous Mode 30.1.1. EUSART Asynchronous Transmitter 30.1.1.1. Enabling the Transmitter 30.1.1.2. Transmitting Data 30.1.1.3. Transmit Data Polarity 30.1.1.4. Transmit Interrupt Flag 30.1.1.5. TSR Status 30.1.1.6. Transmitting 9-Bit Characters 30.1.1.7. Asynchronous Transmission Setup 30.1.2. EUSART Asynchronous Receiver 30.1.2.1. Enabling the Receiver 30.1.2.2. Receiving Data 30.1.2.3. Receive Interrupts 30.1.2.4. Receive Framing Error 30.1.2.5. Receive Overrun Error 30.1.2.6. Receiving 9-Bit Characters 30.1.2.7. Address Detection 30.1.2.8. Asynchronous Reception Setup 30.1.2.9. 9-Bit Address Detection Mode Setup 30.2. Clock Accuracy with Asynchronous Operation 30.3. EUSART Baud Rate Generator (BRG) 30.3.1. Auto-Baud Detect 30.3.2. Auto-Baud Overflow 30.3.3. Auto-Wake-Up on Break 30.3.3.1. Special Considerations 30.3.4. Break Character Sequence 30.3.4.1. Break and Sync Transmit Sequence 30.3.5. Receiving a Break Character 30.4. EUSART Synchronous Mode 30.4.1. Synchronous Host Mode 30.4.1.1. Host Clock 30.4.1.2. Clock Polarity 30.4.1.3. Synchronous Host Transmission 30.4.1.4. Synchronous Host Transmission Setup 30.4.1.5. Synchronous Host Reception 30.4.1.6. Client Clock 30.4.1.7. Receive Overrun Error 30.4.1.8. Receiving 9-Bit Characters 30.4.1.9. Synchronous Host Reception Setup 30.4.2. Synchronous Client Mode 30.4.2.1. EUSART Synchronous Client Transmit 30.4.2.2. Synchronous Client Transmission Setup 30.4.2.3. EUSART Synchronous Client Reception 30.4.2.4. Synchronous Client Reception Setup 30.5. EUSART Operation During Sleep 30.5.1. Synchronous Receive During Sleep 30.5.2. Synchronous Transmit During Sleep 30.6. Register Definitions: EUSART Control 30.6.1. TXxSTA 30.6.2. RCxSTA 30.6.3. BAUDxCON 30.6.4. RCxREG 30.6.5. TXxREG 30.6.6. SPxBRG 30.7. Register Summary - EUSART 31. ADC - Analog-to-Digital Converter with Computation Module 31.1. ADC Configuration 31.1.1. Port Configuration 31.1.2. Channel Selection 31.1.2.1. Channel Grouping 31.1.3. ADC Voltage Reference 31.1.4. Conversion Clock 31.1.5. Interrupts 31.1.6. Result Formatting 31.2. ADC Operation 31.2.1. Starting a Conversion 31.2.2. Completion of a Conversion 31.2.3. ADC Operation During Sleep 31.2.4. External Trigger During Sleep 31.2.5. Auto-Conversion Trigger 31.2.6. ADC Conversion Procedure (Basic Mode) 31.3. ADC Acquisition Requirements 31.4. Computation Operation 31.4.1. Digital Filter/Average 31.4.2. Basic Mode 31.4.3. Accumulate Mode 31.4.4. Average Mode 31.4.5. Burst Average Mode 31.4.6. Low-Pass Filter Mode 31.4.7. Threshold Comparison 31.4.8. Repetition and Sampling Options 31.4.8.1. Continuous Sampling Mode 31.4.8.2. Double Sample Conversion 31.4.9. Capacitive Voltage Divider (CVD) Features 31.4.9.1. CVD Operation 31.4.9.2. Precharge Control 31.4.9.3. Acquisition Control for CVD (ADPRE > 0) 31.4.9.4. Guard Ring Outputs 31.4.9.5. Additional Sample-and-Hold Capacitance 31.5. Register Definitions: ADC Control 31.5.1. ADCON0 31.5.2. ADCON1 31.5.3. ADCON2 31.5.4. ADCON3 31.5.5. ADSTAT 31.5.6. ADCLK 31.5.7. ADREF 31.5.8. ADPCH 31.5.9. ADPRE 31.5.10. ADACQ 31.5.11. ADCAP 31.5.12. ADRPT 31.5.13. ADCNT 31.5.14. ADFLTR 31.5.15. ADRES 31.5.16. ADPREV 31.5.17. ADACC 31.5.18. ADSTPT 31.5.19. ADERR 31.5.20. ADLTH 31.5.21. ADUTH 31.5.22. ADACT 31.5.23. ADCGxA 31.5.24. ADCGxB 31.5.25. ADCGxC 31.5.26. ADCGxD 31.5.27. ADCGxE 31.6. Register Summary - ADC 32. DAC - Digital-to-Analog Converter Module 32.1. Output Voltage Selection 32.2. Ratiometric Output Level 32.3. Buffered DAC Output Range Selection 32.4. Operation During Sleep 32.5. Effects of a Reset 32.6. Register Definitions: DAC Control 32.6.1. DACxCON 32.6.2. DACxDATL 32.7. Register Summary - DAC 33. CMP - Comparator Module 33.1. Comparator Overview 33.2. Comparator Control 33.2.1. Comparator Enable 33.2.2. Comparator Output 33.2.3. Comparator Output Polarity 33.3. Comparator Output Synchronization 33.4. Comparator Hysteresis 33.5. Comparator Interrupt 33.6. Comparator Positive Input Selection 33.7. Comparator Negative Input Selection 33.8. Comparator Response Time 33.9. Analog Input Connection Considerations 33.10. Operation in Sleep Mode 33.11. ADC Auto-Trigger Source 33.12. Register Definitions: Comparator Control 33.12.1. CMxCON0 33.12.2. CMxCON1 33.12.3. CMxNCH 33.12.4. CMxPCH 33.12.5. CMOUT 33.13. Register Summary - Comparator 34. FVR - Fixed Voltage Reference 34.1. Independent Gain Amplifiers 34.2. FVR Stabilization Period 34.3. Register Definitions: FVR 34.3.1. FVRCON 34.4. Register Summary - FVR 35. Temperature Indicator Module 35.1. Module Operation 35.1.1. Temperature Indicator Range 35.1.2. Minimum Operating VDD 35.2. Temperature Calculation 35.3. ADC Acquisition Time 35.4. Register Definitions: Temperature Indicator 35.4.1. FVRCON 35.5. Register Summary - Temperature Indicator 36. ZCD - Zero-Cross Detection Module 36.1. External Resistor Selection 36.2. ZCD Logic Output 36.3. ZCD Logic Polarity 36.4. ZCD Interrupts 36.5. Correction for ZCPINV Offset 36.5.1. Correction by AC Coupling 36.5.2. Correction by Offset Current 36.6. Handling VPEAK Variations 36.7. Operation During Sleep 36.8. Effects of a Reset 36.9. Disabling the ZCD Module 36.10. Register Definitions: ZCD Control 36.10.1. ZCDCON 36.11. Register Summary - ZCD 37. Charge Pump 37.1. Manually Enabled 37.2. Automatically Enabled 37.3. Disabled 37.4. Charge Pump Oscillator 37.5. Charge Pump Threshold 37.6. Charge Pump Ready 37.7. Register Definitions: Charge Pump 37.7.1. CPCON 37.8. Register Summary - Charge Pump 38. Instruction Set Summary 38.1. Read-Modify-Write Operations 38.2. Standard Instruction Set 38.2.1. Standard Instruction Set 39. ICSP™ - In-Circuit Serial Programming™ 39.1. High-Voltage Programming Entry Mode 39.2. Low-Voltage Programming Entry Mode 39.3. Common Programming Interfaces 40. Register Summary 41. Electrical Specifications 41.1. Absolute Maximum Ratings(†) 41.2. Standard Operating Conditions 41.3. DC Characteristics 41.3.1. Supply Voltage 41.3.2. Supply Current (IDD)(1,2) 41.3.3. Power-Down Current (IPD)(1,2,3) 41.3.4. I/O Ports 41.3.5. Memory Programming Specifications 41.3.6. Thermal Characteristics 41.4. AC Characteristics 41.4.1. External Clock/Oscillator Timing Requirements 41.4.2. Internal Oscillator Parameters(1) 41.4.3. I/O and CLKOUT Timing Specifications 41.4.4. Timer0 and Timer1 External Clock Requirements 41.4.5. Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications 41.4.6. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 41.4.7. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 41.4.8. 8-Bit DAC Specifications 41.4.9. Comparator Specifications 41.4.10. Zero-Cross Detect (ZCD) Specifications 41.4.11. Fixed Voltage Reference (FVR) Specifications 41.4.12. Temperature Indicator Requirements 41.4.13. Capture/Compare/PWM Requirements (CCP) 41.4.14. EUSART Synchronous Transmission Requirements 41.4.15. EUSART Synchronous Receive Requirements 41.4.16. SPI Mode Requirements 41.4.17. I2C Bus Start/Stop Bits Requirements 41.4.18. I2C Bus Data Requirements 41.4.19. Configurable Logic Cell (CLC) Characteristics 42. DC and AC Characteristics Graphs and Tables 43. Packaging Information 43.1. Package Details 44. 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