Datasheet ADG714, ADG715 (Analog Devices) - 10

制造商Analog Devices
描述CMOS, Low Voltage Serially Controlled, Octal SPST Switches
页数 / 页21 / 10 — ADG714/. ADG715. Data Sheet. PIN CONFIGURATIONS AND FUNCTION …
修订版E
文件格式/大小PDF / 368 Kb
文件语言英语

ADG714/. ADG715. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. SCLK. SYNC. RESET. DIN. DOUT. GND. VSS. ADG714. TOP VIEW

ADG714/ ADG715 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK SYNC RESET DIN DOUT GND VSS ADG714 TOP VIEW

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ADG714/ ADG715 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK 1 24 SYNC V 2 23 RESET DD DIN 3 22 DOUT GND 4 21 VSS S1 5 20 ADG714 S8 TOP VIEW D1 6 19 (Not to Scale) D8 S2 7 18 S7 D2 8 17 D7 S3 9 16 S6 D3 10 15 D6 S4 11 14 S5
005
D4 12 13 D5
00043- Figure 5. ADG714 TSSOP Pin Configuration
Table 8. ADG714 Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices accommodate serial input rates of up to 30 MHz. 2 VDD Positive Analog Supply Voltage. 3 DIN Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input. 4 GND Ground Reference. 5, 7, 9, 11, 14, 16, 18, 20 Sx Source. These pins may be an input or an output. 6, 8, 10, 12, 13, 15, 17, 19 Dx Drain. These pins may be an input or an output. 21 VSS Negative Analog Supply Voltage. For single-supply operation, tie this pin to ground. 22 DOUT Serial Data Output. This pin allows a number of devices to be daisy-chained. Data is clocked out of the input shift register on the rising edge of SCLK. DOUT is an open-drain output that is pulled to the supply with an external pull-up resistor. 23 RESET Active Low Control Input. This pin clears the input register and turns all switches to the off condition. 24 SYNC Active Low Control Input. This pin is the frame synchronization signal for the input data. When SYNC goes low, this pin powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the falling edges of the following clock cycle. Taking SYNC high updates the switches. Rev. E | Page 10 of 21 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications 5 V Single Supply 3 V Single Supply ±2.5 V Dual Supply Timing Characteristics ADG714 ADG715 Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Power-On Reset Serial Interface 3-Wire Serial Interface 2-Wire Serial Interface Input Shift Register Write Operation Read Operation Applications Information Multiple Devices on One Bus Daisy-Chaining Multiple ADG714 Devices Power Supply Sequencing Decoding Multiple ADG714 Devices Using the ADG739 Outline Dimensions Ordering Guide