Datasheet ADG726, ADG732 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 16-/32-Channel, 4 Ω, +1.8 V to +5.5 V and ±2.5 V Analog Multiplexers |
| 页数 / 页 | 21 / 10 — ADG726/ADG732. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTION … |
| 修订版 | C |
| 文件格式/大小 | PDF / 350 Kb |
| 文件语言 | 英语 |
ADG726/ADG732. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP. 48 47 46 45 44 43 42 41 40 39 38 37. S12A
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ADG726/ADG732 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP A A A A 3 4 5 6 C C 6B 5B 4B 3B S1 S1 S1 S1 NI DA NI DB S1 S1 S1 S1 48 47 46 45 44 43 42 41 40 39 38 37 S12A 36 1 S12B S11A 35 2 S11B S10A 34 3 S10B S9A 33 4 S9B S8A 32 5 S8B S7A ADG726 31 6 S7B S6A TOP VIEW 30 S6B 7 (Not to Scale) S5A 29 8 S5B S4A 28 S4B 9 S3A 27 10 S3B S2A 26 11 S2B S1A 25 12 S1B 13 14 15 16 17 18 19 20 21 22 23 24 A B D DD DD A0 A1 A2 A3 SS V V WR EN V CS CS GN
5
NOTES
-00 5
1. NIC = NOT INTERNALLY CONNECTED. DO NOT CONNECT TO THIS PIN.
7602 Figure 4. ADG726 Pin Configuration
Table 6. ADG726 Pi n Function Description Pin No. Mnemonic Description
1 to 12, 45 to 48 S16A to S1A Source Terminal. This pin may be an input or output. 13, 14 VDD Most Positive Power Supply Potential. 15 to 18 A0 to A3 Logic Control Inputs. 19 CSA Chip Select Pin A. CSA is active low. If a differential output configuration is required, tie CSA and CSB together. 20 CSB Chip Select Pin B. CSB is active low. If a differential output configuration is required, tie CSB and CSA together. 21 WR Write pin. When WR is low, the logic control inputs (A0 to A3) control which state the switches are in. On the rising edge of WR, the logic control input data is latched. 22 EN Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR . 23 GND Ground (0 V) Reference. 24 VSS Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin to GND. 25 to 40 S1B to S16B Source Terminal. This pin may be an input or output. 41 DB Drain Terminal. This pin may be an input or output. 42, 44 NIC Not Internally Connected. Do not connect to this pin. 43 DA Drain Terminal. This pin may be an input or output. Rev. C | Page 10 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS +5 V SINGLE SUPPLY +3 V SINGLE SUPPLY ±2.5 V DUAL SUPPLY TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP 48-LEAD LFCSP Truth Tables TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE
5
NOTES
-00 5
1. NIC = NOT INTERNALLY CONNECTED. DO NOT CONNECT TO THIS PIN.
7602 Figure 4. ADG726 Pin Configuration
Table 6. ADG726 Pi n Function Description Pin No. Mnemonic Description
1 to 12, 45 to 48 S16A to S1A Source Terminal. This pin may be an input or output. 13, 14 VDD Most Positive Power Supply Potential. 15 to 18 A0 to A3 Logic Control Inputs. 19 CSA Chip Select Pin A. CSA is active low. If a differential output configuration is required, tie CSA and CSB together. 20 CSB Chip Select Pin B. CSB is active low. If a differential output configuration is required, tie CSB and CSA together. 21 WR Write pin. When WR is low, the logic control inputs (A0 to A3) control which state the switches are in. On the rising edge of WR, the logic control input data is latched. 22 EN Active Low, Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, the Ax logic control inputs determine the on switches. The EN input signal is not latched by WR . 23 GND Ground (0 V) Reference. 24 VSS Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect this pin to GND. 25 to 40 S1B to S16B Source Terminal. This pin may be an input or output. 41 DB Drain Terminal. This pin may be an input or output. 42, 44 NIC Not Internally Connected. Do not connect to this pin. 43 DA Drain Terminal. This pin may be an input or output. Rev. C | Page 10 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS +5 V SINGLE SUPPLY +3 V SINGLE SUPPLY ±2.5 V DUAL SUPPLY TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTION 48-LEAD TQFP 48-LEAD LFCSP Truth Tables TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE