Datasheet PMG1-S0 (Infineon) - 6
| 制造商 | Infineon |
| 描述 | Power Delivery Microcontroller Gen1 |
| 页数 / 页 | 34 / 6 — PMG1-S0 Datasheet. Block Diagram. PMG1-S0 MCU. Color Key:Power Modes. … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
PMG1-S0 Datasheet. Block Diagram. PMG1-S0 MCU. Color Key:Power Modes. CYPM1011-24LQXI. System Resources. Power. Clocks. Test. Reset
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文件文字版本
PMG1-S0 Datasheet Block Diagram PMG1-S0 MCU Color Key:Power Modes CYPM1011-24LQXI
Active/Sleep Deep Sleep
System Resources
LK)
Power Clocks
Sleep Control ILO IMO ck (PC POR REF Clock Control ckage Pa PWRSYS WDT eral clo N O Matrix F WIC riph -Q ble I/ 4
Test
Pe
Reset
Test Mode Entry ramma g Reset Control Digital DFT 2 OVT), 2 Pro g Analog DFT din s (inclu
USB PD Subsystem
IO m P e
CPU Subsystem
ct (MMIO) 12 G syst ub 2x PFET Gate Drivers terconne S SWD/TC l In IO hera Cortex M0 48 MHz Perip FAST MUL yer AHB) NVIC, IRQMUX La SPCIF gle Flash ESD 64 KB ect (Sin EC Read Accelerator terconn Pads, I SRAM 8 KB System In SRAM Controller ROM 8 KB ROM Controller Document Number: 002-31596 Rev. *B Page 5 of 33 Document Outline PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S0 General Description Features Type-C Support and USB-PD Support Legacy/Proprietary Charging Block System-Level Fault Protection 32-bit MCU Subsystem Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview MCU Subsystem CPU Flash SROM USB-PD Subsystem (SS) USB-PD Physical Layer ADC Charger Detection VBUS Undervoltage and Overvoltage Protection VBUS Short Protection PFET Gate Drivers on VBUS Path VBUS Discharge FETs Integrated Digital Blocks Serial Communication Blocks (SCB) Timer/Counter/PWM Block (TCPWM) I/O Subsystem Power Systems Overview Pinouts Application Diagram Electrical Specifications Absolute Maximum Ratings Device-Level Specifications I/O Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-Speed Oscillator Power Down Gate Driver Specifications Analog to Digital Converter Memory Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
Active/Sleep Deep Sleep
System Resources
LK)
Power Clocks
Sleep Control ILO IMO ck (PC POR REF Clock Control ckage Pa PWRSYS WDT eral clo N O Matrix F WIC riph -Q ble I/ 4
Test
Pe
Reset
Test Mode Entry ramma g Reset Control Digital DFT 2 OVT), 2 Pro g Analog DFT din s (inclu
USB PD Subsystem
IO m P e
CPU Subsystem
ct (MMIO) 12 G syst ub 2x PFET Gate Drivers terconne S SWD/TC l In IO hera Cortex M0 48 MHz Perip FAST MUL yer AHB) NVIC, IRQMUX La SPCIF gle Flash ESD 64 KB ect (Sin EC Read Accelerator terconn Pads, I SRAM 8 KB System In SRAM Controller ROM 8 KB ROM Controller Document Number: 002-31596 Rev. *B Page 5 of 33 Document Outline PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S0 General Description Features Type-C Support and USB-PD Support Legacy/Proprietary Charging Block System-Level Fault Protection 32-bit MCU Subsystem Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview MCU Subsystem CPU Flash SROM USB-PD Subsystem (SS) USB-PD Physical Layer ADC Charger Detection VBUS Undervoltage and Overvoltage Protection VBUS Short Protection PFET Gate Drivers on VBUS Path VBUS Discharge FETs Integrated Digital Blocks Serial Communication Blocks (SCB) Timer/Counter/PWM Block (TCPWM) I/O Subsystem Power Systems Overview Pinouts Application Diagram Electrical Specifications Absolute Maximum Ratings Device-Level Specifications I/O Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-Speed Oscillator Power Down Gate Driver Specifications Analog to Digital Converter Memory Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support