Datasheet PMG1-S0 (Infineon) - 2

link to page 2
PMG1-S0 Datasheet
Power Delivery Microcontroller Gen1
PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description
PMG1 (Power Delivery Microcontroller Gen1) is a family of high-voltage USB-C power delivery (PD) microcontrollers (MCU). These chips include an Arm® Cortex®-M0/M0+ CPU and USB-C PD controller along with analog and digital peripherals. PMG1 is targeted for any embedded system that provides/consumes powers to/from a high-voltage USB-C PD port and leverages the microcontroller to provide additional control capability. Figure 1 shows the PMG1 family segmentation.
Figure 1. PMG1 Family Segmentation
Flash / RAM Feature
PMG1-S3* PMG1-S3*
USB, Crypto, LDO, 1x PD Sink/ 2x PD Sink/ 256KB / NFET Gate Drivers, Source, Source, 32KB Capsense, 12-bit ADC, 28V VBUS, 28V VBUS, SCB, TCPWM 48-QFN 97-BGA
PMG1-S2
USB, Crypto, LDO, 1x PD Sink/ NFET Gate Drivers, 128KB / Source, 8-bit ADC, SCB, 8KB 21.5V VBUS, TCPWM 40-QFN
PMG1-S1
1x PD Sink/ LDO, 128KB / Source, PFET Gate Drivers, 12KB 21.5V VBUS, 8-bit ADC, SCB, 40-QFN TCPWM
PMG1-S0
LDO, 64KB / 1x PD Sink, PFET Gate Drivers, 8KB 21.5V VBUS, 8-bit ADC, SCB, 24-QFN TCPWM < 15 < 20 < 25 < 30 < 55 GPIO# M0 M0+ *Contact your local Cypress sales office for more information on PMG1-S3.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-31596 Rev. *B Revised May 27, 2021 Document Outline PMG1-S0 Datasheet, Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S0 General Description Features Type-C Support and USB-PD Support Legacy/Proprietary Charging Block System-Level Fault Protection 32-bit MCU Subsystem Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and PMG1 SDK Functional Overview MCU Subsystem CPU Flash SROM USB-PD Subsystem (SS) USB-PD Physical Layer ADC Charger Detection VBUS Undervoltage and Overvoltage Protection VBUS Short Protection PFET Gate Drivers on VBUS Path VBUS Discharge FETs Integrated Digital Blocks Serial Communication Blocks (SCB) Timer/Counter/PWM Block (TCPWM) I/O Subsystem Power Systems Overview Pinouts Application Diagram Electrical Specifications Absolute Maximum Ratings Device-Level Specifications I/O Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-Speed Oscillator Power Down Gate Driver Specifications Analog to Digital Converter Memory Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support