Datasheet ADIN1100 (Analog Devices) - 4

ADIN1100 Preliminary Technical Data SPECIFICATIONS
AVDD_H = AVDD_L = VDDIO = 3.3 V; DVDD_1P1 from internal LDO (DVDD_1P1 = DLDO_1P1); Al specifications at −40°C to +105°C, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS Supply Voltage Range AVDD_H 3.13 3.3 3.46 V 2.4 V pk-pk or 1.0 V pk-pk Transmit Level AVDD_L 1.71 1.8/3.3 3.46 V AVDD_H, AVDD_L 1.71 1.8 3.46 V 1.0 V pk-pk Transmit Level DVDD_1P1 1.0 1.1 1.2 V VDDIO 1.71 1.8/2.5 3.46 V /3.3 1.0 V pk-pk Transmit Level (Single AVDD_H = AVDD_L = VDDIO = 1.8 V Supply) DVDD_1P1 = DLDO_1P1 Supply Current, AIDD 25 mA Power Consumption 45 mW 100% data throughput, full activity 1.0 V pk-pk Transmit Level (Dual AVDD_H = AVDD_L = VDDIO = 1.8 V Supply) DVDD_1P1 = External 1.1 V Supply Current, AIDD 16 mA Supply Current, DIDD 9 mA Power Consumption 39 mW 100% data throughput, full activity 2.4 V pk-pk Transmit Level (Single AVDD_H = AVDD_L = VDDIO = 3.3 V Supply) DVDD_1P1 = DLDO_1P1 Supply Current, AIDD 33 mA Power Consumption 109 mW 100% data throughput, full activity 2.4 V pk-pk Transmit Level (Dual AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V Supply) DVDD_1P1 = DLDO_1P1 Supply Current, AIDD 16.5 mA Supply Current, IDDIO 15 mA Power Consumption 81 mW 100% data throughput, full activity 2.4 V pk-pk Transmit Level (Triple AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V Supply) DVDD_1P1 = External 1.1 V Supply Current, AIDD 16.5 mA Supply Current, IDDIO 6 mA Supply Current, DIDD 9 mA Power Consumption 75 mW 100% data throughput, full activity TIMING/LATENCY

MII Latency TX Latency <1.8 μs 18 bit frames RX Latency <3.2 μs 32 bit frames Total Latency ≤5 μs DIGITAL INPUTS/OUTPUTS Applies to MAC interface pins, MDC, MDIO, INT_N, LINK_ST, RESET_N and LED VDDIO = 3.3 V Input Low Voltage (VIL) 0.8 V Input High Voltage (VIH) 2.0 V Output Low Voltage (VOL) 0.4 V Output low current (IOL) (min) = 4 mA Output High Voltage (VOH) 2.4 V Output high current (IOH) (min) = 4 mA VDDIO = 2.5 V VIL 0.7 V VIH 1.7 V VOL 0.4 V IOL (min) = 4 mA Rev. PrG | Page 4 of 70 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Characteristics Power-Up Timing Management Interface Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Theory of Operation Power Supply Domains MAC Interface MII Interface Mode RMII Interface Mode RGMII Interface Mode Auto-Negotiation Transmit Amplitude Resolution Master/Slave Resolution Management Interface Interrupt (INT_N) MDI Interface Reset Operation Power-On Reset Hardware Reset Software Reset PHY Subsystem Reset MAC Interface Reset Status LEDs LED Function Link Status Pin Powerdown Modes Hardware Powerdown Mode Software Powerdown Mode Hardware Configuration Pins Hardware Configuration Pin Functions PHY Address Configuration Software Powerdown after Reset Master/Slave Preference Transmit Amplitude MAC Interface Selection Media Convertor Bringing Up 10BASE-T1L Links Unmanaged PHY Operation Managed PHY Operation Power-up and Reset Complete Configuring the Part for Linking Advertisement of Transmit Level Operating Mode Advertisement of Master/Slave Successful Completion of Auto-Negotiation Link Status On-Chip Diagnostics Loopback Modes PMA Loopback PCS Loopback MAC Interface Loopback MAC Interface Remote Loopback External MII/RMII Loopback Frame Generator and Checker Frame Generator and Checker used with Remote Loopback with Two PHYs Test Modes Accessing the test modes Applications Information System Level Power Management Transmit Level = 1.0 V pk-pk Transmit Level = 2.4 V pk-pk Component Recommendations Crystal External Clock Input Register Summary Clause 22 Clause 45 Recommended Register Operation Latch Low Registers IEEE Duplicated Registers Read Modify Write Operation Clause 22 Register Details MII Control Register MII Status Register PHY Identifier 1 Register PHY Identifier 2 Register MMD Access Control Register MMD Access Register Clause 45 Register Details PMA/PMD Control 1 Register PMA/PMD Status 1 Register PMA/PMD MMD Devices in Package 1 Register PMA/PMD MMD Devices in Package 2 Register PMA/PMD Control 2 Register PMA/PMD Status 2 Register PMA/PMD Transmit Disable Register PMA/PMD Extended Abilities Register BASE-T1 PMA/PMD Extended Ability Register BASE-T1 PMA/PMD Control Register 10BASE-T1L PMA Control Register 10BASE-T1L PMA Status Register 10BASE-T1L Test Mode Control Register Frequency Offset Saturation Threshold for CR Stability Check Register Slave IIR Filter Change Echo Acquisition Clock Recovery Proportional Gain Register 10BASE-T1L PMA Link Status Register MSE Value Register PCS Control 1 Register PCS Status 1 Register PCS MMD Devices in Package 1 Register PCS MMD Devices in Package 2 Register PCS Status 2 Register 10BASE-T1L PCS Control Register 10BASE-T1L PCS Status Register AUTO-_NEGOTIATION MMD Devices in Package 1 Register AUTO-_NEGOTIATION MMD Devices in Package 2 Register BASE-T1 Autonegotiation Control Register BASE-T1 Autonegotiation Status Register BASE-T1 Autonegotiation Advertisement [15:0] Register BASE-T1 Autonegotiation Advertisement [31:16] Register BASE-T1 Autonegotiation Advertisement [47:32] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [47:32] Register BASE-T1 Autonegotiation Next Page Transmit [15:0] Register BASE-T1 Autonegotiation Next Page Transmit [31:16] Register BASE-T1 Autonegotiation Next Page Transmit [47:32] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [47:32] Register 10BASE-T1 Autonegotiation Control Register 10BASE-T1 Autonegotiation Status Register Extra Autonegotiation Status Register PHY Instantaneous Status Register Vendor Specific MMD 1 Device Identifier High Register Vendor Specific MMD 1 Device Identifier Low Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific MMD 1 Status Register System Interrupt Status Register System Interrupt Mask Register Software Reset Register Software Power-down Control Register PHY Subsystem Reset Register PHY MAC Interface Reset Register System Status Register CRSM Power Management Control Register MAC Interface Configuration Register CRSM Diagnostics Clock Control Register Package Configuration Values Register MDIO Control Register Pinmux Configuration 1 Register Pinmux Configuration 2 Register LED 0 ON/_OFF Blink Time Register LED 1 ON/_OFF Blink Time Register LED Control Register LED Polarity Register Vendor Specific MMD 2 Device Identifier High Register Vendor Specific MMD 2 Device Identifier Low Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific MMD 2 Status Register PHY Subsystem Interrupt Status Register PHY Subsystem Interrupt Mask Register Frame Checker Enable Register Frame Checker Interrupt Enable Register Frame Checker Transmit Select Register Receive Error Count Register Frame Checker Count High Register Frame Checker Count Low Register Frame Checker Length Error Count Register Frame Checker Alignment Error Count Register Frame Checker Symbol Error Count Register Frame Checker Oversized Frame Count Register Frame Checker Undersized Frame Count Register Frame Checker Odd Nibble Frame Count Register Frame Checker Odd Preamble Packet Count Register Frame Checker False Carrier Count Register Frame Generator Enable Register Frame Generator CONTROL/_RESTART Register Frame Generator Continuous Mode Enable Register Frame Generator Interrupt Enable Register Frame Generator Frame Length Register Frame Generator Number of Frames High Register Frame Generator Number of Frames Low Register Frame Generator Done Register RMII Configuration Register MAC Interface Loopbacks Configuration Register MAC Start Of Packet (SOP) Generation Control Register PCB Layout Recommendations PHY Package Layout Component Placement Crystal Placement and Routing Outline Dimensions