Datasheet VCNL36825T (Vishay) - 4
| 制造商 | Vishay |
| 描述 | Proximity Sensor With Interrupt, VCSEL, and I2C Interface |
| 页数 / 页 | 16 / 4 — VCNL36825T. I2C BUS TIMING CHARACTERISTICS. STANDARD MODE. FAST MODE. … |
| 文件格式/大小 | PDF / 238 Kb |
| 文件语言 | 英语 |
VCNL36825T. I2C BUS TIMING CHARACTERISTICS. STANDARD MODE. FAST MODE. PARAMETER. SYMBOL. UNIT. MIN. MAX. Note
该数据表的模型线
文件文字版本
VCNL36825T
www.vishay.com Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS
(Tamb = 25 °C, unless otherwise specified)
STANDARD MODE FAST MODE PARAMETER SYMBOL UNIT MIN. MAX. MIN. MAX.
Clock frequency f(I2CCLK) 10 100 10 400 kHz Bus free time between start and stop condition t(BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; t after this period, the first clock is generated (HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t(SUSTA) 4.7 - 0.6 - μs Stop condition setup time t(SUSTO) 4.0 - 0.6 - μs Data hold time t(HDDAT) 0 3450 0 900 ns Data setup time t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Clock / data fall time t(f) - 300 - 300 ns Clock / data rise time t(r) - 1000 - 300 ns
Note
• Data based on standard I2C protocol requirement, not tested in production t t t (LOW) (r) (f) VIH I2C BUS CLOCK VIL (SCLK) t t t (HDSTA) (HIGH) (SUSTA) t(SUSTO) t(BUF) t t (HDDAT) (SUDAT) I2C BUS VIH DATA (SDAT) VIL { { { { P S S P Stop condition Start condition Start Stop t(LOSEXT) SCLK SDA ACK ACK t t t (LOWMEXT) (LOWMEXT) (LOWMEXT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) Fig. 1 - I2C Bus Timing Diagram Rev. 1.2, 22-Mar-2021
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Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS
(Tamb = 25 °C, unless otherwise specified)
STANDARD MODE FAST MODE PARAMETER SYMBOL UNIT MIN. MAX. MIN. MAX.
Clock frequency f(I2CCLK) 10 100 10 400 kHz Bus free time between start and stop condition t(BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; t after this period, the first clock is generated (HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t(SUSTA) 4.7 - 0.6 - μs Stop condition setup time t(SUSTO) 4.0 - 0.6 - μs Data hold time t(HDDAT) 0 3450 0 900 ns Data setup time t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Clock / data fall time t(f) - 300 - 300 ns Clock / data rise time t(r) - 1000 - 300 ns
Note
• Data based on standard I2C protocol requirement, not tested in production t t t (LOW) (r) (f) VIH I2C BUS CLOCK VIL (SCLK) t t t (HDSTA) (HIGH) (SUSTA) t(SUSTO) t(BUF) t t (HDDAT) (SUDAT) I2C BUS VIH DATA (SDAT) VIL { { { { P S S P Stop condition Start condition Start Stop t(LOSEXT) SCLK SDA ACK ACK t t t (LOWMEXT) (LOWMEXT) (LOWMEXT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) Fig. 1 - I2C Bus Timing Diagram Rev. 1.2, 22-Mar-2021
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Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000