Datasheet L6981 (STMicroelectronics) - 3
| 制造商 | STMicroelectronics |
| 描述 | 38 V, 1.5 A synchronous step-down converter with low quiescent current |
| 页数 / 页 | 49 / 3 — L6981. Pin configuration. Figure 2. Pin connection (top view). Table 1. … |
| 文件格式/大小 | PDF / 3.5 Mb |
| 文件语言 | 英语 |
L6981. Pin configuration. Figure 2. Pin connection (top view). Table 1. Pin description. Pin #. Symbol. Function. DS13554. Rev 1
该数据表的模型线
文件文字版本
L6981 Pin configuration 2 Pin configuration Figure 2. Pin connection (top view)
1 8 SW PGND 2 7 BOOT VIN 3 6 VCC AGND 4 5 FB/VOUT EN/CLKIN(*) (*) Synchronization is allowed for LNM versions only.
Table 1. Pin description Pin # Symbol Function
1 SW Switching node Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The 2 BOOT gate charge required to drive the internal NMOS is refreshed during the low side switch conduction time. This pin supplies the embedded analog circuitry. Connect a ceramic capacitor 3 VCC (≥ 1 µF) to filter internal voltage reference. 4 FB/VOUT FB is output voltage sensing with eternal voltage divider Enable pin with internal voltage divider. Pull down/up to disable/enable the device. 5 EN/CLKIN In LNM versions, this pin is also used to provide an external clock signal, which synchronizes the device. 6 AGND Analog ground 7 VIN DC input voltage 8 PGND Power ground
DS13554
-
Rev 1 page 3/49
Document Outline 1 Diagram 2 Pin configuration 3 Typical application circuit 4 Absolute maximum ratings 5 Electrical characteristics 6 Functional description 6.1 Enable 6.2 Soft-start 6.3 Undervoltage lockout 6.4 Light-load operation 6.4.1 Low consumption mode (LCM) 6.4.2 Low noise mode (LNM) 6.4.3 Efficiency for Low consumption mode and Low noise mode part number 6.4.4 Load regulation for low consumption mode and low noise mode part number 6.5 Overvoltage protection 6.5.1 Low consumption mode part number 6.5.2 Low noise mode part number 6.6 Overcurrent protection 6.7 Thermal shutdown 7 Closing the loop 7.1 GCO(s) control to output transfer function 7.2 Error amplifier compensation network 7.3 Voltage divider 8 Design of the power components 8.1 Programmable power up threshold 8.2 External synchronization (only available for Low Noise Mode) 8.3 Output voltage adjustment 8.4 Design of the power components 8.4.1 Input capacitor selection 8.4.2 Inductor selection 8.4.3 Output capacitor selection 9 Application board 10 Efficiency curves 11 Thermal dissipation 12 Package information 12.1 SO 8L package information 13 Ordering information Revision history
1 8 SW PGND 2 7 BOOT VIN 3 6 VCC AGND 4 5 FB/VOUT EN/CLKIN(*) (*) Synchronization is allowed for LNM versions only.
Table 1. Pin description Pin # Symbol Function
1 SW Switching node Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The 2 BOOT gate charge required to drive the internal NMOS is refreshed during the low side switch conduction time. This pin supplies the embedded analog circuitry. Connect a ceramic capacitor 3 VCC (≥ 1 µF) to filter internal voltage reference. 4 FB/VOUT FB is output voltage sensing with eternal voltage divider Enable pin with internal voltage divider. Pull down/up to disable/enable the device. 5 EN/CLKIN In LNM versions, this pin is also used to provide an external clock signal, which synchronizes the device. 6 AGND Analog ground 7 VIN DC input voltage 8 PGND Power ground
DS13554
-
Rev 1 page 3/49
Document Outline 1 Diagram 2 Pin configuration 3 Typical application circuit 4 Absolute maximum ratings 5 Electrical characteristics 6 Functional description 6.1 Enable 6.2 Soft-start 6.3 Undervoltage lockout 6.4 Light-load operation 6.4.1 Low consumption mode (LCM) 6.4.2 Low noise mode (LNM) 6.4.3 Efficiency for Low consumption mode and Low noise mode part number 6.4.4 Load regulation for low consumption mode and low noise mode part number 6.5 Overvoltage protection 6.5.1 Low consumption mode part number 6.5.2 Low noise mode part number 6.6 Overcurrent protection 6.7 Thermal shutdown 7 Closing the loop 7.1 GCO(s) control to output transfer function 7.2 Error amplifier compensation network 7.3 Voltage divider 8 Design of the power components 8.1 Programmable power up threshold 8.2 External synchronization (only available for Low Noise Mode) 8.3 Output voltage adjustment 8.4 Design of the power components 8.4.1 Input capacitor selection 8.4.2 Inductor selection 8.4.3 Output capacitor selection 9 Application board 10 Efficiency curves 11 Thermal dissipation 12 Package information 12.1 SO 8L package information 13 Ordering information Revision history