Datasheet LM73100 (Texas Instruments) - 36
| 制造商 | Texas Instruments |
| 描述 | 2.7 -23 V, 5.5 A Integrated Ideal Diode with Input Reverse Polarity and Overvoltage Protection |
| 页数 / 页 | 52 / 36 — LM7310. www.ti.com. LM73100. TPS259470L. Figure 8-11. USB PD Port … |
| 文件格式/大小 | PDF / 5.1 Mb |
| 文件语言 | 英语 |
LM7310. www.ti.com. LM73100. TPS259470L. Figure 8-11. USB PD Port Protection
该数据表的模型线
文件文字版本
LM7310
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
www.ti.com
V = 5 V to 20 V OUT OUT IN OVLO
LM73100
PGTH IMON R dVdt IMON GND EN/UVLO PG V = 5 V to 20V BUS CDVDT PD Controller VLOGIC OVLO EN/UVLO FLT V = 5 V to 20 V IN OUT IN
TPS259470L
AUXOFF ITIMER dVdt GND ILM C RILM ITIMER CDVDT
Figure 8-11. USB PD Port Protection
The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from one power source to the other during fast or slow ramp of either supply. The following waveforms illustrate the LM73100 reverse current blocking behavior in USB applications. 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM7310 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
www.ti.com
V = 5 V to 20 V OUT OUT IN OVLO
LM73100
PGTH IMON R dVdt IMON GND EN/UVLO PG V = 5 V to 20V BUS CDVDT PD Controller VLOGIC OVLO EN/UVLO FLT V = 5 V to 20 V IN OUT IN
TPS259470L
AUXOFF ITIMER dVdt GND ILM C RILM ITIMER CDVDT
Figure 8-11. USB PD Port Protection
The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from one power source to the other during fast or slow ramp of either supply. The following waveforms illustrate the LM73100 reverse current blocking behavior in USB applications. 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM7310 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information