Datasheet AD8306 (Analog Devices) - 9

AD8306
the intercept to –108 dBV, by raising the RSSI output voltage for range: a 60 Hz hum, picked up due to poor grounding tech- zero input, and to provide temperature compensation, resulting niques; spurious coupling from digital logic on the same PC in a stable intercept. For zero signal conditions, all the detector board; a strong EMI source; etc. output currents are equal. For a finite input, of either polarity, Very careful shielding is essential to guard against such un- their difference is converted by the output interface to a single- wanted signals, and also to minimize the likelihood of instability sided voltage nominally scaled 20 mV/dB (400 mV per decade), at due to HF feedback from the limiter outputs to the input. With the output VLOG (Pin 16). This scaling is controlled by a sepa- this in mind, the minimum possible limiter gain should be used. rate feedback stage, having a tightly controlled transcon- Where only the logarithmic amplifier (RSSI) function is re- ductance. A small uncertainty in the log slope and intercept quired, the limiter should be disabled by omitting RLIM and remains (see Specifications); the intercept may be adjusted (see tying the outputs LMHI and LMLO directly to VPS2. A good Applications). ground plane should be used to provide a low impedance con- nection to the common pins, for the decoupling capacitor(s)
VPS2
used at VPS1 and VPS2, and at the output ground. Note that
ISOURCE
COM2 is a special ground pin serving just the RSSI output.
CURRENT >50mA MIRROR 1.3k SUMMED
V
1.3k ON DEMAND
V The four pins labeled PADL tie down directly to the metallic
FLTR DETECTOR OUTPUTS
lead frame, and are thus connected to the back of the chip. The
C1 LGP C
process on which the AD8306 is fabricated uses a bonded-wafer
3.5pF F
technique to provide a silicon-on-insulator isolation, and there is
LGN VLOG I
no junction or other dc path from the back side to the circuitry
SINK 20mV/dB IT 3.3k
V
3.3k
V
FIXED
on the surface. These paddle pins must be connected directly to
1mA
the ground plane using the shortest possible lead lengths to
VLOG 125
m
A 250
m
s
minimize inductance.
COMM TRANSCONDUCTANCE
The voltages at the two supply pins should not be allowed to
DETERMINES SLOPE
differ greatly; up to 500 mV is permissible. It is desirable to Figure 23. Simplified RSSI Output Interface allow VPS1 to be slightly more negative than VPS2. When the primary supply is greater than 2.7 V, the decoupling resistors R1 The RSSI output bandwidth, fLP, is nominally 3.5 MHz. This is and R2 (Figure 24) may be increased to improve the isolation controlled by the compensation capacitor C1, which may be and lower the dissipation in the IC. However, since VPS2 sup- increased by adding an external capacitor, CF, between FLTR ports the RSSI load current, which may be large, the value of (Pin 10) and VLOG (Pin 16). An external 33 pF will reduce fLP R2 should take this into account. to 350 kHz, while 360 pF will set it to 35 kHz, in each case with an essentially one-pole response. In general, the relationships
Basic Connections for Log (RSSI) Output
(for f Figure 24 shows the connections required for most applications. LP in MHz) are: The AD8306 is enabled by connecting ENBL to VPS1. The × 10 – 12 7 . × − 12 7 10 10 6 . device is put into the sleep mode by grounding this pin. The C = – 3 5 . ; = F pF fLP + (1) inputs are ac-coupled by C1 and C2, which normally should fLP CF 3 5 . pF have the same value (CC). The input is, in this case, terminated Using a load resistance of 50 Ω or greater, and at any tempera- with a 52.3 Ω resistor that combines with the AD8306’s input ture, the peak output voltage may be at least 2.4 V when using a resistance of 1000 Ω to give a broadband input impedance of supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is 50 Ω. Alternatively an input matching network can be used (see consistent with the maximum permissible input levels. The incre- Input Matching section). mental output resistance is approximately 0.3 Ω at low frequen- cies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.
VS (2.7V TO 6.5V) R1 R2
The output is unconditionally stable with load capacitance, but
10
V
10
V
1 COM2 VLOG 16 RSSI
it should be noted that while the peak sourcing current is
0.1
m
F 0.1
m
F
over 100 mA, and able to rapidly charge even large capacitances,
2 VPS1 VPS2 15
the internally provided sinking current is only 1 mA. Thus, the
C1 3 PADL PADL 14
fall time from the 2 V level will be as long as 2 µs for a 1 nF
0.01
m
F AD8306 4 INHI LMHI 13
load. This may be reduced by adding a grounded load resistance.
SIGNAL RT INPUTS 52.3
V
5 INLO LMLO 12 CF (OPTIONAL USING THE AD8306 C2 SEE TEXT) 0.01
m
F 6 PADL PADL 11
The AD8306 exhibits very high gain from 1 MHz to over 1 GHz,
10
at which frequency the gain of the main path is still over 65 dB.
7 COM1 FLTR
Consequently, it is susceptible to all signals, within this very
ENABLE 8 ENBL LMDR 9
broad frequency range, that find their way to the input termi- nals. It is important to remember that these are quite indistin- Figure 24. Basic Connections for RSSI (Log) Output guishable from the “wanted” signal, and will have the effect of The 0.01 µF coupling capacitors and the resulting 50 Ω input raising the apparent noise floor (that is, lowering the useful impedance give a high-pass corner frequency of around 600 kHz. dynamic range). Therefore, while the signal of interest may be (1/(2 π RC)), where C = (C1)/2. In high frequency applications, an IF of, say, 200 MHz, any of the following could easily be this corner frequency should be placed as high as possible, to larger than this signal at the lower extremities of its dynamic minimize the coupling of unwanted low frequency signals. In REV. A –9–