Datasheet AD8317 (Analog Devices) - 16

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AD8317 Data Sheet EVALUATION BOARD Table 5. Evaluation Board (Rev. A) Configuration Options Component Function Default Conditions
VPOS, GND Supply and Ground Connections. Not applicable R1, C1, C2 Input Interface. R1 = 52.3 Ω (Size 0402) The 52.3 Ω resistor in Position R1 combines with the internal input impedance C1 = 47 nF (Size 0402) of the AD8317 to give a broadband input impedance of about 50 Ω. C1 and C2 C2 = 47 nF (Size 0402) are dc-blocking capacitors. A reactive impedance match can be implemented by replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors. R5, R7 Temperature Compensation Interface. R5 = 200 Ω (Size 0402) The internal temperature compensation network is optimized for input signals R7 = open (Size 0402) up to 3.6 GHz when R7 is 10 kΩ. This circuit can be adjusted to optimize performance for other input frequencies by changing the value of the resistor in Position R7. See Table 4 for specific RTADJ resistor values. R2, R3, R4, R6, RL, CL Output Interface—Measurement Mode. R2 = 0 Ω (Size 0402) In measurement mode, a portion of the output voltage is fed back to the VSET R3 = open (Size 0402) pin via R2. The magnitude of the slope of the VOUT output voltage response R4 = open (Size 0402) can be increased by reducing the portion of VOUT that is fed back to VSET. R6 R6 = 1 kΩ (Size 0402) can be used as a back-terminating resistor or as part of a single-pole, low-pass RL = CL = open (Size 0402) filter. R2, R3 Output Interface—Controller Mode. R2 = open (Size 0402) In this mode, R2 must be open. In controller mode, the AD8317 can control the R3 = open (Size 0402) gain of an external component. A setpoint voltage is applied to Pin VSET, the value of which corresponds to the desired RF input signal level applied to the AD8317 RF input. A sample of the RF output signal from this variable gain component is selected, typically via a directional coupler, and applied to the AD8317 RF input. The voltage at the VOUT pin is applied to the gain control of the variable gain element. A control voltage is applied to the VSET pin. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising R2 and R3, or a capacitor can be installed in Position R3 to form a low-pass filter along with R2. C4, C5 Power Supply Decoupling. C4 = 0.1 μF (Size 0603) The nominal supply decoupling consists of a 100 pF filter capacitor placed C5 = 100 pF (Size 0402) physically close to the AD8317 and a 0.1 μF capacitor placed nearer to the power supply input pin. C3 Filter Capacitor. C3 = 8.2 pF (Size 0402) The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the AD8317 for pulsed input signals. See the Output Filtering section for more details.
VPOS TADJ GND C4 R5 0.1µF 200Ω VOUT_ALT C5 R4 R7 OPEN 100pF OPEN C1 R6 VOUT 47nF 1kΩ CL RL 8 7 6 5 OPEN OPEN INLO VPOS TADJ VOUT R1 R2 AD8317 52.3Ω 0Ω INHI COMM CLPF VSET 1 2 3 4 RFIN C2 C3 VSET 8.2pF 47nF R3 OPEN
034 1- 54 05 Figure 36. Evaluation Board Schematic Rev. D | Page 16 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8317 BASIC CONNECTIONS INPUT SIGNAL COUPLING OUTPUT INTERFACE SETPOINT INTERFACE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE MEASUREMENT MODE SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE CONTROLLER MODE OUTPUT FILTERING OPERATION BEYOND 8 GHz EVALUATION BOARD DIE INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE