Datasheet AD8317 (Analog Devices) - 13

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Data Sheet AD8317
For example, PINTERCEPT for a sinusoidal input signal expressed in between VOUT and the RF input signal when the device is in terms of dBm (decibels referred to 1 mW), in a 50 Ω system is measurement mode, the AD8317 adjusts the voltage on VOUT P (VOUT is now an error amplifier output) until the level at the INTERCEPT [dBm] = P 2 RF input corresponds to the applied VSET. When the AD8317 INTERCEPT [dBV] − 10 × log10(Z0 × 1 mW/1 VRMS ) = 2 dBV − 10 × log operates in controller mode, there is no defined relationship 10(50 × 10−3) = 15 dBm (8) between the VSET and the VOUT voltage; VOUT settles to a value For a square wave input signal in a 200 Ω system, that results in the correct input signal level appearing at PINTERCEPT = INHI/INLO. −1 dBV − 10 × log 2 10[(200 Ω × 1 mW/1 VRMS )] = 6 dBm For this output power control loop to be stable, a ground- Further information on the intercept variation dependence referenced capacitor must be connected to the CLPF pin. This upon waveform can be found in the AD8313 and AD8307 capacitor, CFLT, integrates the error signal (in the form of a data sheets. current) to set the loop bandwidth and ensure loop stability.
SETTING THE OUTPUT SLOPE IN MEASUREMENT
Further details on control loop dynamics can be found in the
MODE
AD8315 data sheet. To operate in measurement mode, VOUT must be connected to VSET. Connecting VOUT directly to VSET yields the nominal
VGA/VVA RFIN
logarithmic slope of approximately −22 mV/dB. The output
DIRECTIONAL COUPLER
swing corresponding to the specified input range is then approx-
GAIN CONTROL
imately 0.35 V to 1.7 V. The slope and output swing can be
ATTENUATOR VOLTAGE
increased by placing a resistor divider between VOUT and
47nF VOUT
VSET (that is, one resistor from VOUT to VSET and one
INHI
resistor from VSET to ground). The input impedance of VSET
AD8317 52.3Ω
is approximately 40 kΩ. To prevent this input impedance from
VSET DAC INLO
affecting the resulting slope, keep slope-setting resistors below
47nF CLPF
20 kΩ. If two equal resistors are used (for example, 10 kΩ/10 kΩ), 9 02
CFLT
1- the slope doubles to approximately −44 mV/dB. 54 05 Figure 29. Controller Mode
AD8317 VOUT –44mV/dB
Decreasing VSET, which corresponds to demanding a higher
10kΩ
signal from the VGA, increases VOUT. The gain control voltage
VSET
of the VGA must have a positive sense. A positive control
10kΩ
028 voltage to the VGA increases the gain of the device. 1- 54 05 The basic connections for operating the AD8317 in an auto- Figure 28. Increasing the Slope matic gain control (AGC) loop with the ADL5330 are shown in
CONTROLLER MODE
Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a large gain control range of 60 dB with ±0.5 dB gain stability. The AD8317 provides a controller mode feature at the VOUT This configuration is similar to Figure 29. pin. By using VSET for the setpoint voltage, it is possible for the AD8317 to control subsystems, such as power amplifiers (PAs), The gain of the ADL5330 is controlled by the output pin of the variable gain amplifiers (VGAs), or variable voltage attenuators AD8317. This voltage, VOUT, has a range of 0 V to near VPOS. To (VVAs), that have output power that increases monotonically avoid overdrive recovery issues, the AD8317 output voltage can with respect to their gain control signal. be scaled down using a resistive divider to interface with the 0 V to 1.4 V gain control range of the ADL5330. To operate in controller mode, the link between VSET and VOUT is broken. A setpoint voltage is applied to the VSET A coupler/attenuation of 21 dB is used to match the desired input, VOUT is connected to the gain control terminal of the maximum output power from the VGA to the top end of the VGA, and the RF input of the detector is connected to the linear operating range of the AD8317 (approximately −5 dBm output of the VGA (usually using a directional coupler and at 900 MHz). some additional attenuation). Based on the defined relationship Rev. D | Page 13 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8317 BASIC CONNECTIONS INPUT SIGNAL COUPLING OUTPUT INTERFACE SETPOINT INTERFACE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE MEASUREMENT MODE SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE CONTROLLER MODE OUTPUT FILTERING OPERATION BEYOND 8 GHz EVALUATION BOARD DIE INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE