link to page 14 link to page 14 link to page 14 link to page 15 link to page 7 link to page 14 HMC1144Data SheetAPPLICATIONS INFORMATION The HMC1144 is a GaAs, pHEMT, MMIC power amplifier. The VDD = 4 V and IDD = 320 mA bias conditions are the operating Capacitive bypassing is required for VDD1A through VDD4A and points recommended to optimize the overall performance. Unless VDD1B through VDD4B (see Figure 38). VGG1B is the gate bias otherwise noted, the data shown was taken using the recomm- pad for all four gain stages. Apply a gate bias voltage to VGG1B ended bias condition. Operation of the HMC1144 at different and use capacitive bypassing as shown in Figure 38. bias conditions may provide performance that differs from All measurements for this device were taken using the typical what is shown in the Typical Performance Characteristics application circuit (see Figure 38) and configured as shown in section. Biasing the HMC1144 for higher drain current the assembly diagram (see Figure 40). typically results in higher P1dB, output IP3, and gain, but at the expense of increased power consumption. The following is the recommended bias sequence during power-up: ALTERNATE BIASING CONFIGURATION 1. Connect to ground. It is possible to bias the gate from the north (instead of the 2. Set the gate bias voltage to −2 V. south) and bias the drain from the south (instead of the north). 3. Set all the drain bias voltages, V Although this alternate bias configuration was not measured DD = 4 V. 4. Increase the gate bias voltage to achieve a quiescent during production testing and was evaluated minimally during current, I product validation, it does offer flexibility in cases where it is DD = 320 mA. 5. Apply the RF signal. more convenient to have the gate and drain bias approach the die from a different direction (see Figure 39). The following is the recommended bias sequence during In the alternate bias configuration, capacitive bypassing is power-down: required for the VGG1A pad to which the bias voltage is applied, 1. Turn off the RF signal. as well as for all eight VDDxA/VDDxB pads. 2. Decrease the gate bias voltage to −2 V to achieve IDD = 0 mA (approximately). 3. Decrease all of the drain bias voltages to 0 V. 4. Increase the gate bias voltage to 0 V. VDD1AVDD2AVDD3AVDD4AVDD1BVDD2BVDD3BVDD4BRFINRFOUT1A1B2A2B3A3B4A4B 1 VGG1A 02 43- V 131 GG1B Figure 35. Simplified Block Diagram Rev. D | Page 12 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS 35 GHz TO 40 GHz FREQUENCY RANGE 40 GHz TO 50 GHz FREQUENCY RANGE 50 GHz TO 70 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ALTERNATE BIASING CONFIGURATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE