Datasheet BUK9V13-40H (Nexperia) - 3
| 制造商 | Nexperia |
| 描述 | Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) |
| 页数 / 页 | 13 / 3 — Nexperia. BUK9V13-40H. Dual N-channel 40 V, 13 mOhm logic level MOSFET in … |
| 修订版 | 11022021 |
| 文件格式/大小 | PDF / 313 Kb |
| 文件语言 | 英语 |
Nexperia. BUK9V13-40H. Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration)
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Nexperia BUK9V13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 8. Limiting values Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit Limiting values FET1 and FET2
VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VGS gate-source voltage DC; Tj = 25 °C -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 46 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 42 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 30 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 169 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C
Source-drain diode FET1 and FET2
IS source current Tmb = 25 °C - 42 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 169 A
Avalanche ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain- ID = 39.9 A; Vsup ≤ 40 V; RGS = 50 Ω; [2] [3] - 10.6 mJ source avalanche energy VGS = 10 V; Tj(init) = 25 °C; Fig. 4 IAS non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C; [4] - 39.9 A current RGS = 50 Ω; Fig. 4 [1] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [3] Refer to application note AN10273 for further information. [4] Protected by 100% test 03aa16 120 aaa-032340 50 ID (A ( ) A Pder (%) 40 80 30 20 40 10 0 0 0 50 100 150 200 0 25 50 75 100 125 150 175 200 Tmb (°C) Tmb (°C) VGS ≥ 10 V 42A continuous current has been successfully demonstrated during application tests. Practically
Fig. 1. Normalized total power dissipation as a
the current will be limited by PCB, thermal design
function of mounting base temperature
and operating temperature.
Fig. 2. Continuous drain current as a function of mounting base temperature, FET1 and FET2
BUK9V13-40H All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. Al rights reserved
Product data sheet 11 February 2021 3 / 13
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents
Nexperia BUK9V13-40H Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56D (half-bridge configuration) 8. Limiting values Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit Limiting values FET1 and FET2
VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VGS gate-source voltage DC; Tj = 25 °C -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 46 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 42 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 30 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 169 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C
Source-drain diode FET1 and FET2
IS source current Tmb = 25 °C - 42 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 169 A
Avalanche ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain- ID = 39.9 A; Vsup ≤ 40 V; RGS = 50 Ω; [2] [3] - 10.6 mJ source avalanche energy VGS = 10 V; Tj(init) = 25 °C; Fig. 4 IAS non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C; [4] - 39.9 A current RGS = 50 Ω; Fig. 4 [1] 42A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [3] Refer to application note AN10273 for further information. [4] Protected by 100% test 03aa16 120 aaa-032340 50 ID (A ( ) A Pder (%) 40 80 30 20 40 10 0 0 0 50 100 150 200 0 25 50 75 100 125 150 175 200 Tmb (°C) Tmb (°C) VGS ≥ 10 V 42A continuous current has been successfully demonstrated during application tests. Practically
Fig. 1. Normalized total power dissipation as a
the current will be limited by PCB, thermal design
function of mounting base temperature
and operating temperature.
Fig. 2. Continuous drain current as a function of mounting base temperature, FET1 and FET2
BUK9V13-40H All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. Al rights reserved
Product data sheet 11 February 2021 3 / 13
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents