Datasheet STM32WB5MMG (STMicroelectronics) - 6
| 制造商 | STMicroelectronics |
| 描述 | Bluetooth Low Energy 5.0 and 802.15.4 module |
| 页数 / 页 | 31 / 6 — STM32WB5MMG. Pin description. Table 1. STM32WB5MMG pin/ball definition. … |
| 文件格式/大小 | PDF / 3.7 Mb |
| 文件语言 | 英语 |
STM32WB5MMG. Pin description. Table 1. STM32WB5MMG pin/ball definition. Pin name. Pin name (function after reset). Pin type
该数据表的模型线
文件文字版本
STM32WB5MMG Pin description Table 1. STM32WB5MMG pin/ball definition Pin name Pin name (function after reset) Pin type STM32WB5MMG STM32WB55VGY
1 F6 PA2 I/O 2 G6 PA1 I/O 3 G7 PA0 I/O 4 H8 VREF+ S 5 J9 VSS S 6 H9 VDDA S 7 G10 PC3 I/O 8 G9 PC2 I/O 9 G8 PC1 I/O 10 F9 NRST I/O 11 F10 PB9 I/O 12 F8 PC0 I/O 13 E8 PH3-BOOT0 I/O 14 F7 PB8 I/O 15 C10 VBAT S 16 F1 VSSSMPS S 17 D1 VDDSMPS S 18 D7 PB7 I/O 19 D6 PB5 I/O 20 C7 PB4 I/O 21 A9 PB3 I/O 22 A6 PC10 I/O 23 B6 PC11 I/O 24 C5 PC12 I/O 25 A5 PA13 I/O 26 A3 PA14 I/O 27 A4 PA15 I/O 28 B5 PA10 I/O 29 A2 PA12 I/O 30 A1 PA11 I/O 31 - VSS S 32 B3 VDDUSB S 33 C4 PD0 I/O 34 C3 PD1 I/O 35 C1 PB13 I/O 36 D2 PC6 I/O 37 E2 PB14 I/O 38 F3 PB15 I/O 39 F5 PB6 I/O 40 G5 PC13 I/O 41 G3 PB12 I/O 42 G1 PE4 I/O 45 H5 PC5 I/O 46 J6 PB11 I/O
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Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures
1 F6 PA2 I/O 2 G6 PA1 I/O 3 G7 PA0 I/O 4 H8 VREF+ S 5 J9 VSS S 6 H9 VDDA S 7 G10 PC3 I/O 8 G9 PC2 I/O 9 G8 PC1 I/O 10 F9 NRST I/O 11 F10 PB9 I/O 12 F8 PC0 I/O 13 E8 PH3-BOOT0 I/O 14 F7 PB8 I/O 15 C10 VBAT S 16 F1 VSSSMPS S 17 D1 VDDSMPS S 18 D7 PB7 I/O 19 D6 PB5 I/O 20 C7 PB4 I/O 21 A9 PB3 I/O 22 A6 PC10 I/O 23 B6 PC11 I/O 24 C5 PC12 I/O 25 A5 PA13 I/O 26 A3 PA14 I/O 27 A4 PA15 I/O 28 B5 PA10 I/O 29 A2 PA12 I/O 30 A1 PA11 I/O 31 - VSS S 32 B3 VDDUSB S 33 C4 PD0 I/O 34 C3 PD1 I/O 35 C1 PB13 I/O 36 D2 PC6 I/O 37 E2 PB14 I/O 38 F3 PB15 I/O 39 F5 PB6 I/O 40 G5 PC13 I/O 41 G3 PB12 I/O 42 G1 PE4 I/O 45 H5 PC5 I/O 46 J6 PB11 I/O
DS13252
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Rev 1 page 6/31
Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures