Datasheet STM32WB5MMG (STMicroelectronics) - 21

STM32WB5MMG SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86
The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.
Figure 13. SiP-LGA86 marking example
Product identification(1) 32WB5M 2D matrix code MGH6TR Certification marking Y WW Date code Pin 1 indentifier 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS13252
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Rev 1 page 21/31
Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures