Datasheet SAMA5D3 (Microchip) - 1772

SAMA5D3 SERIES
Table 60-4:
Issue Date SAMA5D3 Datasheet Rev. 11121E Revision History (Continued)
Comments
Section 10. “ARM Cortex-A5” (cont’d)
Section 10.1 “Description”:
-deleted sentence “The design can include the FPU only, in which case the Media Processing Engine (MPE) is not
included.”
-at end of section, added “Note: All ARM publications referenced in this datasheet can be found at www.arm.com.”
(hyperlink to www.arm.com replaces previous mulitple links to individual ARM publications)
Section 10. “Debug and Test”: no substantive changes
Section 11. “Standard Boot Strategies”
Section 11.1 “Description”:
-“If BMS signal is tied to 0, BMS_BIT is read at 1” changed to “If BMS signal is tied to 0, BMS_BIT is read at 0”
-“If BMS signal is tied to 1, BMS_BIT is read at 0” changed to “If BMS signal is tied to 1, BMS_BIT is read at 1”
Section 11.4.1 “NVM Boot Sequence”: corrected register name “Boot Sequence Configuration Register” to “Boot
Sequence Controller Configuration Register”
At end of Section 11.4.3.1 “ARM Exception Vectors Check”, inserted a space after each “B” in the example of valid
vectors
Section 11.4.4.4 “SPI Flash Boot”: replaced sentence “The SPI Flash Boot program supports all Atmel DataFlash
devices” with “The SPI Flash Boot program supports the DataFlash devices listed in Table 11-2”
Table 11-2 "DataFlash Devices": added device AT45DB641
Section 11.5.3.2 “USB Class”: in first paragraph, replaced phrase “from Windows 98SE® to Windows 7®” with
“beginning with Windows 98SE®
Section 13. “Boot Sequence Controller (BSC)” 03-Feb-15 Throughout, corrected register name “Boot Sequence Configuration Register” to “Boot Sequence Controller
Configuration Register”
Section 13.1 “Description”: reworded first paragraph
Section 13.4.1 “Boot Sequence Controller Configuration Register”: updated BOOT field description
Section 14. “AXI Bus Matrix (AXIMX)”
Updated Section 14.2 “Embedded Characteristics”
Revised Section 14.3.1 “Remap”
Section 15. “Bus Matrix (MATRIX)”
Throughout, changed “securizable” to “secured” or “securable” as required by context
Section 15.2 “Embedded Characteristics”: replaced bullet “Write Protection of User Interface Registers” with “Register
Write Protection”
Section 15.3 “Memory Mapping”: deleted redundant/duplicated sentence “The Bus Matrix user interface provides
Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently” from
end of section
Latency Quality of Service text added in Section 15.8.2 “Arbitration Priority Scheme”
Table 15-2 "Register Mapping": reset value of PRAS and PRBS registers changed to 0x00000000
Section 15.9 “Register Write Protection”: updated title (was “Write Protect Registers”) and revised content
Section 15.10.1 “Bus Matrix Master Configuration Registers”: reformatted ULBT field description as table
Section 15.10.2 “Bus Matrix Slave Configuration Registers”: reformatted DEFMSTR_TYPE field description as table
LQOSENx bits added in Section 15.10.3 “Bus Matrix Priority Registers A For Slaves” and Section 15.10.4 “Bus Matrix
Priority Registers B For Slaves”
”Section 15.10.7 “Write Protection Mode Register”: updated title; updated content below bitmap
Section 15.10.8 “Write Protection Status Register”: updated title; updated content below bitmap  2020 Microchip Technology Inc. DS60001609B-page 1773