Datasheet SAMA5D3 (Microchip) - 1771
| 制造商 | Microchip |
| 描述 | Low-Power Arm Cortex -A5 Processor-Based MPU, 536 MHz, FPU, Gigabit Ethernet with IEEE 1588 plus 10/100 Ethernet, Dual CAN, AES, SHA |
| 页数 / 页 | 1818 / 1771 — SAMA5D3 SERIES Table 60-4:. Issue Date SAMA5D3 Datasheet Rev. 11121E … |
| 文件格式/大小 | PDF / 30.1 Mb |
| 文件语言 | 英语 |
SAMA5D3 SERIES Table 60-4:. Issue Date SAMA5D3 Datasheet Rev. 11121E Revision History. Comments
该数据表的模型线
文件文字版本
SAMA5D3 SERIES Table 60-4:
Issue Date SAMA5D3 Datasheet Rev. 11121E Revision History
Comments
Formatting, spelling and editorial changes throughout document
Section “Description”: no substantive changes
Section 1. “Features”
In GMAC and EMAC bullets, replaced “MAC Controller” with “Ethernet Media Access Controller”
Added detail to USART feature
Section 2. “Block Diagram”
Figure 2-1. "SAMA5D3 Block Diagram": added DMA to DBGU block
Section 3. “Signal Description”: no substantive changes
Section 4. “Package and Pinout”
Table 4-1 “SAMA5D3 Pinout for 324-ball LFBGA Package”: for ball R5, corrected direction of GTXCK signal from
input to output
Table 4-2 “SAMA5D3 Pinout for 324-ball TFBGA Package”: for ball AB1, corrected direction of GTXCK signal from
input to output
Section 5. “Power Considerations”
Table 5-1 “SAMA5D3 Power Supplies”:
-in VDDUTMIC “Powers” comments, deleted instance of “The UTMI PLL”
-updated VDDANA voltage range 03-Feb-15 -in VDDFUSE “Powers” comments, added sentence “It must be powered for Fuse programming and to switch in
Secure Mode.”
Revised Section 5.2 “Power-Up Considerations”
Revised Section 5.3 “Power-Down Considerations”
Section 6. “Memories”:
Section 6.1.2 “Internal ROM”: in last paragraph, corrected register name “Boot Select Control Register” to “Boot
Sequence Controller Configuration Register”
Section 6.1.3 “Boot Strategies”: corrected application note title “Secure Boot on SAMA5D3 Series” to “SAMA5D3x
Secure Boot Strategy”
Section 7. “Real-time Event Management”: no substantive changes
Section 8. “System Controller”
Section 8-1 “SAMA5D3 System Controller Block Diagram”: corrected PMC output "pck[0-1]" to "pck[0–2]"
Section 8.2 “Backup Section”:
-changed bullet “SCKR register” to “Slow Clock Controller Configuration Register (SCKC_CR)”
-changed bullet “Boot Select Control Register” to “Sequence Controller Configuration (BSC_CR)”
Section 9. “Peripherals”: no substantive changes
Section 10. “ARM Cortex-A5”
Replaced instances of “ARM Architecture Reference Manual” with “ARM Architecture Reference Manual, ARMv7-A
and ARMv7-R edition” DS60001609B-page 1772 2020 Microchip Technology Inc.
Issue Date SAMA5D3 Datasheet Rev. 11121E Revision History
Comments
Formatting, spelling and editorial changes throughout document
Section “Description”: no substantive changes
Section 1. “Features”
In GMAC and EMAC bullets, replaced “MAC Controller” with “Ethernet Media Access Controller”
Added detail to USART feature
Section 2. “Block Diagram”
Figure 2-1. "SAMA5D3 Block Diagram": added DMA to DBGU block
Section 3. “Signal Description”: no substantive changes
Section 4. “Package and Pinout”
Table 4-1 “SAMA5D3 Pinout for 324-ball LFBGA Package”: for ball R5, corrected direction of GTXCK signal from
input to output
Table 4-2 “SAMA5D3 Pinout for 324-ball TFBGA Package”: for ball AB1, corrected direction of GTXCK signal from
input to output
Section 5. “Power Considerations”
Table 5-1 “SAMA5D3 Power Supplies”:
-in VDDUTMIC “Powers” comments, deleted instance of “The UTMI PLL”
-updated VDDANA voltage range 03-Feb-15 -in VDDFUSE “Powers” comments, added sentence “It must be powered for Fuse programming and to switch in
Secure Mode.”
Revised Section 5.2 “Power-Up Considerations”
Revised Section 5.3 “Power-Down Considerations”
Section 6. “Memories”:
Section 6.1.2 “Internal ROM”: in last paragraph, corrected register name “Boot Select Control Register” to “Boot
Sequence Controller Configuration Register”
Section 6.1.3 “Boot Strategies”: corrected application note title “Secure Boot on SAMA5D3 Series” to “SAMA5D3x
Secure Boot Strategy”
Section 7. “Real-time Event Management”: no substantive changes
Section 8. “System Controller”
Section 8-1 “SAMA5D3 System Controller Block Diagram”: corrected PMC output "pck[0-1]" to "pck[0–2]"
Section 8.2 “Backup Section”:
-changed bullet “SCKR register” to “Slow Clock Controller Configuration Register (SCKC_CR)”
-changed bullet “Boot Select Control Register” to “Sequence Controller Configuration (BSC_CR)”
Section 9. “Peripherals”: no substantive changes
Section 10. “ARM Cortex-A5”
Replaced instances of “ARM Architecture Reference Manual” with “ARM Architecture Reference Manual, ARMv7-A
and ARMv7-R edition” DS60001609B-page 1772 2020 Microchip Technology Inc.