Datasheet SLG47004 (Dialog Semiconductor) - 5
| 制造商 | Dialog Semiconductor |
| 描述 | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| 页数 / 页 | 243 / 5 — SLG47004. Preliminary. Figures. Datasheet. Revision 2.1. 13-Nov-2020 |
| 文件格式/大小 | PDF / 5.6 Mb |
| 文件语言 | 英语 |
SLG47004. Preliminary. Figures. Datasheet. Revision 2.1. 13-Nov-2020
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
Figures
Figure 1: Block Diagram... 11 Figure 2: Steps to Create a Custom GreenPAK Device...38 Figure 3: IO with I2C Mode IO Structure Diagram..40 Figure 4: Matrix OE IO Structure Diagram ...41 Figure 5: IO0 GPI Structure Diagram ...42 Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C ...43 Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ..43 Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C ...44 Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ..44 Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C ...45 Figure 11: Connection Matrix ...46 Figure 12: Connection Matrix Example ..46 Figure 13: 2-bit LUT0 or DFF0 ...53 Figure 14: 2-bit LUT1 or DFF1 ...54 Figure 15: 2-bit LUT2 or DFF2 ...54 Figure 16: DFF Polarity Operations..56 Figure 17: 2-bit LUT3 or PGen...57 Figure 18: PGen Timing Diagram...57 Figure 19: 3-bit LUT0 or DFF3 ...59 Figure 20: 3-bit LUT1 or DFF4 ...60 Figure 21: 3-bit LUT2 or DFF5 ...60 Figure 22: 3-bit LUT3 or DFF6 ...61 Figure 23: 3-bit LUT4 or DFF7 ...61 Figure 25: 3-bit LUT6 or DFF9 ...62 Figure 24: 3-bit LUT5 or DFF8 ...62 Figure 26: DFF Polarity Operations with nReset..65 Figure 27: DFF Polarity Operations with nSet..66 Figure 28: 4-bit LUT0 or DFF10 ...67 Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter..69 Figure 30: Example: Ripple Counter Functionality...70 Figure 31: Possible Connections Inside Multi-Function Macrocell...72 Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1) ...73 Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2) ...74 Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3) ...75 Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4) ...76 Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5) ...77 Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6) ...78 Figure 38: 4-bit LUT1 or CNT/DLY0...82 Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ..84 Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes...85 Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up ..85 Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up ...86 Figure 43: One-Shot Function Timing Diagram..87 Figure 44: Frequency Detection Mode Timing Diagram...88 Figure 45: Edge Detection Mode Timing Diagram ...89 Figure 46: Delayed Edge Detection Mode Timing Diagram ...90 Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ...90 Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ...91 Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ...91 Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ...92 Figure 51: Counter Value, Counter Data = 3..92 Figure 52: Wake and Sleep Control er ...93 Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ...94 Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ..94 Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ...95
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 5 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
Figures
Figure 1: Block Diagram... 11 Figure 2: Steps to Create a Custom GreenPAK Device...38 Figure 3: IO with I2C Mode IO Structure Diagram..40 Figure 4: Matrix OE IO Structure Diagram ...41 Figure 5: IO0 GPI Structure Diagram ...42 Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C ...43 Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ..43 Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C ...44 Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ..44 Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C ...45 Figure 11: Connection Matrix ...46 Figure 12: Connection Matrix Example ..46 Figure 13: 2-bit LUT0 or DFF0 ...53 Figure 14: 2-bit LUT1 or DFF1 ...54 Figure 15: 2-bit LUT2 or DFF2 ...54 Figure 16: DFF Polarity Operations..56 Figure 17: 2-bit LUT3 or PGen...57 Figure 18: PGen Timing Diagram...57 Figure 19: 3-bit LUT0 or DFF3 ...59 Figure 20: 3-bit LUT1 or DFF4 ...60 Figure 21: 3-bit LUT2 or DFF5 ...60 Figure 22: 3-bit LUT3 or DFF6 ...61 Figure 23: 3-bit LUT4 or DFF7 ...61 Figure 25: 3-bit LUT6 or DFF9 ...62 Figure 24: 3-bit LUT5 or DFF8 ...62 Figure 26: DFF Polarity Operations with nReset..65 Figure 27: DFF Polarity Operations with nSet..66 Figure 28: 4-bit LUT0 or DFF10 ...67 Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter..69 Figure 30: Example: Ripple Counter Functionality...70 Figure 31: Possible Connections Inside Multi-Function Macrocell...72 Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1) ...73 Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2) ...74 Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3) ...75 Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4) ...76 Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5) ...77 Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6) ...78 Figure 38: 4-bit LUT1 or CNT/DLY0...82 Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ..84 Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes...85 Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up ..85 Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up ...86 Figure 43: One-Shot Function Timing Diagram..87 Figure 44: Frequency Detection Mode Timing Diagram...88 Figure 45: Edge Detection Mode Timing Diagram ...89 Figure 46: Delayed Edge Detection Mode Timing Diagram ...90 Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ...90 Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ...91 Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ...91 Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ...92 Figure 51: Counter Value, Counter Data = 3..92 Figure 52: Wake and Sleep Control er ...93 Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ...94 Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ..94 Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ...95
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 5 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History