Datasheet ADP1878, ADP1879 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode |
| 页数 / 页 | 40 / 3 — Data Sheet. ADP1878/ADP1879. SPECIFICATIONS. Table 1. Parameter. Symbol. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 2.0 Mb |
| 文件语言 | 英语 |
Data Sheet. ADP1878/ADP1879. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADP1878/ADP1879 SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS High Input Voltage Range VIN C = 22 µF(25 V rating) right at Pin 1 to PGND (Pin 11) VIN ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.95 12 20 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.95 12 20 V ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.25 12 20 V Quiescent Current I + FB = 1.5 V, no switching 1.1 mA Q_REG I Q_BST Shutdown Current I + EN < 600 mV 140 225 µA REG,SD I BST,SD Undervoltage Lockout UVLO Rising VIN (see Figure 35 for temperature variation) 2.65 V UVLO Hysteresis Falling VIN from operational state 178 mV INTERNAL REGULATOR Do not load VREG externally because it is intended to CHARACTERISTICS bias internal circuitry only VREG Operational Output Voltage VREG C = 4.7 µF to PGND, 0.22 µF to GND, V = 2.95 V to 20 V VREG IN ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.75 5 5.5 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.75 5 5.5 V ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.05 5 5.5 V VREG Output in Regulation V = 7 V, 100 mA 4.82 4.981 5.16 V IN V = 12 V, 100 mA 4.83 4.982 5.16 V IN Load Regulation 0 mA to 100 mA, V = 7 V 32 mV IN 0 mA to 100 mA, V = 20 V 34 mV IN Line Regulation V = 7 V to 20 V, 20 mA 1.8 mV IN V = 7 V to 20 V, 100 mA 2.0 mV IN VIN to VREG Dropout Voltage 100 mA out of VREG, V ≤ 5 V 306 415 mV IN Short VREG to PGND V = 20 V 229 320 mA IN SOFT START Connect external capacitor from SS pin to GND, Soft Start Period Calculation C = 10 nF/ms 10 nF/ms SS ERROR AMPLIFER FB Regulation Voltage V T = 25°C 600 mV FB J T = −40°C to +85°C 596 600 604 mV J T = −40°C to +125°C 594.2 600 605.8 mV J Transconductance G 320 496 670 µS m FB Input Leakage Current I FB = 0.6 V, EN = VREG 1 50 nA FB, LEAK CURRENT SENSE AMPLIFIER GAIN Programming Resistor (RES) RES = 47 kΩ ± 1% 2.7 3 3.3 V/V Value from RES to PGND RES = 22 kΩ ± 1% 5.5 6 6.5 V/V RES = none 11 12 13 V/V RES = 100 kΩ ± 1% 22 24 26 V/V SWITCHING FREQUENCY Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation1 ADP1878ACPZ-0.3-R7/ 300 kHz ADP1879ACPZ-0.3-R7 On Time V = 5 V, V = 2 V, T = 25°C 1120 1200 1345 ns IN OUT J Minimum On Time V = 20 V 145 190 ns IN Minimum Off Time 84% duty cycle (maximum) 340 400 ns Rev. B | Page 3 of 40 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Diagram Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout (LDO) Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier ADP1879 Power Saving Mode (PSM) Timer Operation Pseudo Fixed Frequency Power-Good Monitoring Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (Gm) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss MOSFET Switching Loss Body Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current-Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits 12 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Current Application Circuit 300 kHz High Current Application Circuit Packaging and Ordering Information Outline Dimensions Ordering Guide
Data Sheet ADP1878/ADP1879 SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS High Input Voltage Range VIN C = 22 µF(25 V rating) right at Pin 1 to PGND (Pin 11) VIN ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.95 12 20 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.95 12 20 V ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.25 12 20 V Quiescent Current I + FB = 1.5 V, no switching 1.1 mA Q_REG I Q_BST Shutdown Current I + EN < 600 mV 140 225 µA REG,SD I BST,SD Undervoltage Lockout UVLO Rising VIN (see Figure 35 for temperature variation) 2.65 V UVLO Hysteresis Falling VIN from operational state 178 mV INTERNAL REGULATOR Do not load VREG externally because it is intended to CHARACTERISTICS bias internal circuitry only VREG Operational Output Voltage VREG C = 4.7 µF to PGND, 0.22 µF to GND, V = 2.95 V to 20 V VREG IN ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.75 5 5.5 V ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.75 5 5.5 V ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.05 5 5.5 V VREG Output in Regulation V = 7 V, 100 mA 4.82 4.981 5.16 V IN V = 12 V, 100 mA 4.83 4.982 5.16 V IN Load Regulation 0 mA to 100 mA, V = 7 V 32 mV IN 0 mA to 100 mA, V = 20 V 34 mV IN Line Regulation V = 7 V to 20 V, 20 mA 1.8 mV IN V = 7 V to 20 V, 100 mA 2.0 mV IN VIN to VREG Dropout Voltage 100 mA out of VREG, V ≤ 5 V 306 415 mV IN Short VREG to PGND V = 20 V 229 320 mA IN SOFT START Connect external capacitor from SS pin to GND, Soft Start Period Calculation C = 10 nF/ms 10 nF/ms SS ERROR AMPLIFER FB Regulation Voltage V T = 25°C 600 mV FB J T = −40°C to +85°C 596 600 604 mV J T = −40°C to +125°C 594.2 600 605.8 mV J Transconductance G 320 496 670 µS m FB Input Leakage Current I FB = 0.6 V, EN = VREG 1 50 nA FB, LEAK CURRENT SENSE AMPLIFIER GAIN Programming Resistor (RES) RES = 47 kΩ ± 1% 2.7 3 3.3 V/V Value from RES to PGND RES = 22 kΩ ± 1% 5.5 6 6.5 V/V RES = none 11 12 13 V/V RES = 100 kΩ ± 1% 22 24 26 V/V SWITCHING FREQUENCY Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation1 ADP1878ACPZ-0.3-R7/ 300 kHz ADP1879ACPZ-0.3-R7 On Time V = 5 V, V = 2 V, T = 25°C 1120 1200 1345 ns IN OUT J Minimum On Time V = 20 V 145 190 ns IN Minimum Off Time 84% duty cycle (maximum) 340 400 ns Rev. B | Page 3 of 40 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Diagram Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout (LDO) Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier ADP1879 Power Saving Mode (PSM) Timer Operation Pseudo Fixed Frequency Power-Good Monitoring Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (Gm) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss MOSFET Switching Loss Body Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current-Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits 12 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Current Application Circuit 300 kHz High Current Application Circuit Packaging and Ordering Information Outline Dimensions Ordering Guide