Datasheet LTC4162-L (Analog Devices) - 5

制造商Analog Devices
描述35V/3.2A Multi-Cell Lithium-Ion Step-Down Battery Charger with PowerPath and I2C Telemetry
页数 / 页52 / 5 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply …
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ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the full specified

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full specified

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link to page 46 LTC4162-L
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ICHARGE Range 1–32 mV Servo Voltage Resolution (5 Bits) ICHARGE = (VCSP – VCSN)/RSNSB 1 mV (VCSP – VCSN) Accuracy Note 5 –0.25 0.25 mV l –0.75 0.75 mV IINLIM Range 0.5–32 mV Servo Voltage Resolution (6 Bits) IIN = (VCLP – VCLN)/RSNSI 0.5 mV (VCLP – VCLN) Accuracy Note 6 –0.2 0.2 mV VINLIM Range 0.14–36 V Resolution (8 Bits) 140.625 mV Full Scale Accuracy –1 1 % fOSC Switching Frequency RT = 63.4k l 1.4 1.5 1.6 MHz DMAX Maximum Duty Cycle 99.5 % RSWITCH Primary Switch On-Resistance 90 mΩ RRECT Rectifier Switch On-Resistance 90 mΩ IPEAK Peak Inductor Current Limit Note 3 45mV/RSNSB A
System Controls
VIN_UVLO VIN Charger Enable Rising Threshold 4.2 4.4 4.6 V Input Undervoltage Lockout Hysteresis 0.2 V VIN_DUVLO VIN to BATSENS+ Charger Enable Rising Threshold 100 150 200 mV Differential Undervoltage Lockout Hysteresis 170 mV VIN_OVLO VIN Charger Disable Rising Threshold 37.6 38.6 40 V Overvoltage Lockout Hysteresis 1.4 V VINTVCC_UVLO INTVCC Telemetry Enable Rising Threshold 2.75 2.85 2.95 V Undervoltage Lockout Hysteresis 0.12 V
Telemetry A/D Measurement Subsystem
IBAT Resolution IBAT = (VCSP – VCSN)/RSNSB 1.466 µV /LSB (VCSP – VCSN) Offset Error 0.32mV < VCSP – VCSN < 32mV –0.15 0.15 mV Span Error –1.25 1.25 %rdng IIN Resolution IIN = (VCLP – VCLN)/RSNSI 1.466 µV/LSB (VCLP – VCLN) Offset Error 0.32mV < VCLP – VCLN < 32mV –0.15 0.15 mV Span Error –1.25 1.25 %rdng VIN Resolution 1.649 mV/LSB Offset Error 3V < VIN < 35V –25 25 mV Span Error –1 1 %rdng VBATSENS+ Resolution 192.4 µV/LSB (Per cell_count) Offset Error 2V < VBATSENS+ < 4.2V –10 10 mV Span Error –1 1 %rdng VOUT Resolution 1.653 mV/LSB Offset Error 3V < VOUT < 35V –25 25 mV Span Error –1 1 %rdng VNTC/VNTCBIAS Resolution 45.833 µV/V/LSB Offset Error 0 < VNTC/VNTCBIAS < 1 –1 1 mV/V Span Error –1 1 %rdng T_die Resolution 0.0215 °C/LSB Offset –264.4 °C Rev A For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Revision History Typical Application Related Parts