Datasheet LTC4162-S (Analog Devices) - 31

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APPLICATIONS INFORMATION
from that of the current carrying inductor path. The bulk 2.0 load capacitor should be on the inductor side of this connection, not the BATSENS+ side. A smaller ceramic 1.6 capacitor may additionally be added to the BATSENS+ CONSTANT CURRENT pin near the LTC4162. A heavy copper run from the low 1.2 side of battery to the GND (paddle) of the LTC4162 is also necessary to reduce resistance optimizing charging time. 0.8 CONSTANT VOLTAGE PANEL CURRENT (A)
Resistive Inputs and Test Equipment
0.4 Care must be exercised in the laboratory while evaluat- 0.0 ing the LTC4162 with inline ammeters. The combined 0 4 8 12 16 20 24 PANEL VOLTAGE (V) resistance of the internal current sense resistor and fuse 4162S F07 of many meters can be 0.5Ω or more. At currents of 3A+
Figure 7. High Quality 40W Solar Panel
it is possible to drop several volts across the meter and wiring, possibly resulting in unusual voltage readings or When the driving impedance is at or below a few Ohms artificially high switch duty cycles. A resistive connection the LTC4162's input voltage regulation loop is very stable. to the source of input power can be particularly trouble- However, in its attempt to find the maximum power point, some. With the undervoltage limit feature enabled, the the LTC4162 drags the panel voltage down to its constant- switching regulator output power will be automatically current high impedance region. In this region the LTC4162 reduced to prevent VIN from falling below its programmed input voltage control loop will become unstable. To avoid level. This feature greatly improves tolerance to resistive instability and UVLO restarts the real input impedance of input power sources (from either undersized wiring and the LTC4162 should be maintained at about 2.5Ω in the connectors or test equipment) and facilitates stable be- 1kHz to 10kHz band. To achieve this characteristic an R-C havior, but if engaged, could result in much less power network should be added to the solar panel. For example, delivery to the battery. a lower quality 100μF to 1000μF capacitor plus a 2.5Ω series resistor would make a good impedance correction
Solar Panel Input Impedance Correction
network as shown in Figure 8. The maximum power point tracking algorithm uses the LTC4162's input voltage regulation control loop to find and operate at the maximum power point of the solar panel. In general solar panels have two distinct regions of operation roughly corresponding to constant voltage and – + constant current. In its constant voltage region the panel 2.5Ω 0.1µF presents a somewhat low impedance and in its constant + VIN INFET CLP CLN current region a very high impedance. Figure 7 shows an 150µF LTC4162 4162S F08 I-V characteristic collected from a brightly lit high quality 40W solar panel. Notice the very high impedance below
Figure 8. Input Impedance Compensation Network
16V and fairly low impedance above 16V. Figure 9 shows the driving impedance presented by the combined solar panel and 10μF bypass capacitor on VOUT in both low impedance and high impedance solar panel regions. In the low impedance region the aggregate imped- ance characteristic is about one to three Ohms in parallel Rev B For more information www.analog.com 31 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Revision History Typical Application Related Parts