Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 18

link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18 link to page 18
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPECIFICATIONS OPERATING CONDITIONS 266 MHz / 300 MHz / 350 MHz / 400 MHz 450 MHz Parameter1 Description Min Nominal Max Min Nominal Max Unit
V 2 DD_INT Internal (Core) Supply Voltage 1.05 1.10 1.15 SVSNOM – 25 mV 1.00 – 1.15 SVSNOM + 25 mV V VDD_EXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V VDD_THD Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 V V 3 IH High Level Input Voltage at 2.0 3.6 2.0 3.6 V VDD_EXT = Max V 3 IL Low Level Input Voltage at –0.3 +0.8 –0.3 +0.8 V VDD_EXT = Min V 4 IH_CLKIN High Level Input Voltage at 2.2 VDD_EXT 2.2 VDD_EXT V VDD_EXT = Max VIL_CLKIN Low Level Input Voltage at –0.3 +0.8 –0.3 +0.8 V VDD_EXT = Min CONSUMER GRADE TJ Junction Temperature 0 115 N/A5 N/A5 °C 88-Lead LFCSP_VQ TJ Junction Temperature 0 110 N/A5 N/A5 °C 100-Lead LQFP_EP TJ Junction Temperature 0 110 0 115 °C 176-Lead LQFP_EP INDUSTRIAL GRADE TJ Junction Temperature –40 +125 N/A5 N/A5 °C 100-Lead LQFP_EP TJ Junction Temperature –40 +125 N/A5 N/A5 °C 176-Lead LQFP_EP AUTOMOTIVE GRADE6 TJ Junction Temperature –40 +125 N/A5 N/A5 °C 88-Lead LFCSP_VQ TJ Junction Temperature –40 +125 N/A5 N/A5 °C 100-Lead LQFP_EP TJ Junction Temperature –40 +125 N/A5 N/A5 °C 176-Lead LQFP_EP 1 Specifications subject to change without notice. 2 SVSNOM refers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVSNOM value in each chip may be used for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVSNOM values for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357). 3 Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK, MLBCLK, MLBDAT, MLBSIG. 4 Applies to input pins CLKIN, WDT_CLKIN. 5 N/A means not applicable. 6 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information. Rev. H | Page 18 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide