Datasheet HMC860LP3E (Analog Devices)

制造商Analog Devices
描述Quad Low Noise High PSRR Linear Voltage Regulator
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HMC860LP3E. QUAD LOW NOISE HIGH PSRR. LINEAR VOLTAGE REGULATOR. Typical Applications. Features. Functional Diagram

Datasheet HMC860LP3E Analog Devices

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HMC860LP3E
v01.0811
QUAD LOW NOISE HIGH PSRR LINEAR VOLTAGE REGULATOR Typical Applications Features
The HMC860LP3E is ideal for: Ultra Low Noise: 3nV/√Hz at 10 kHz, 7nV/√Hz at 1 kHz • Test Instrumentation High Power Supply Rejection Ratio (PSRR) • Military Radios, Radar and ECM 80 dB at 1 kHz, 60 dB at 1 MHz • Basestation Infrastructure Four Voltage Outputs: • Ultra Low Noise Frequency Generation VR1 @ 3V / 80 mA VR2, VR3 @ 3V / 20 mA • Fractional-N Synthesizer Supply VR4 @ 4.5V / 120 mA • Mixed-Signal Circuit Supply Adjustable Outputs: 2.5V to 5.2V Low Power-Down Current: <1 µA 16 Lead 3x3 mm SMT Package: 9mm²
Functional Diagram General Description
9 The HMC860LP3E is a BiCMOS ultra low noise quad-output voltage regulator. It features a low noise band-gap reference external y decoupled for best in-close noise performance. High Power Supply T Rejection Ratio (PSRR) in the 0.1 MHz to 10 MHz M range provides excel ent rejection of preceding switching regulator noise. The four voltage outputs are ideal for frequency generation subsystems including G - S Hittite’s broad line of PLLs with Integrated VCOs. IN Each output voltage can be adjusted higher or N lower than the default value by using one external resistor. Each output can be set to 5V by grounding IO the corresponding HV pin. The regulator can be IT powered down by the TTL-compatible Enable input. D The HMC860LP3E is housed in a 3x3mm QFN SMT N package. O R C
Electrical Specifications, T = +25 °C
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Parameter Conditions Min Typ Max Units W Default Output Voltage VR1, VR2, VR3 Vdd = 5.5V; Maximum load current 3 3.05 3.1 V O Default Output Voltage VR4 Vdd = 5.5V; Maximum load current 4.4 4.5 4.6 V P Output Voltage Tolerance Vdd = 5.5V; Maximum load current 2 % Input Voltage Range (Default) Default output voltage configuration 4.8 5.6 V E.g.: VR1 = VR2 = VR3 = VR4 = 3.05V; Max (VRx) + Input Voltage Range 5.6 V Vdd, min = 3.35V 0.3V Set by external resistors. Output Voltage Range VR1 to VR4 2.5 5.2 V Vdd = Max(VRx)+0.3V Inf F or o m ra tip o r n ifc ur e n ,is hd e e d lbiv y e A r n y al oa g n D d evi tco e s p is la beclie ev eo d rtd o ebre sa: H ccur iattti e taen M d re ilicarbloew . H a o ve wev eC r, o n r o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other poration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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978-250-3343 tel • 978-250-3373 fax • O rights of third parties that may result from its use. Specifications subject to change without notice. No rd P e h r o nO e n : 7 -li 81 n - e 32 a 9- t 4 w 70 ww. 0 • Ohi rd tt e ite r on.lc inom license is granted by implication or otherwise under any patent or patent rights of Analog Devices. e at www.analog.com Application Trademarks and registered trademarks are the property of their respective owners.Support: apps@ A h ppitlitcitae ti .oco n Sm upport: Phone: 1-800-ANALOG-D