Datasheet ADP7142 (Analog Devices) - 22

ADP7142 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 1.70 2.10 1.60 2.00 SQ 1.50 1.90 0.65 BSC 4 6 PIN 1 INDEX EXPOSED 1.10 AREA PAD 1.00 0.425 0.90 0.350 0.275 0.15 MIN 3 1 TOP VIEW PIN 1 BOTTOM VIE W IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 0.60 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.55 0.05 MAX THE PIN CONFIGURATION AND 0.50 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.35 -D SEATING PLANE 0.30 0.20 REF 18 -20 03581 -0 G 0.25 -17 K P 08
Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP] 2.00 mm × 2.00 mm Body and 0.55 mm Package Height (CP-6-3) Dimensions shown in millimeters
5.00 2.29 4.90 4.80 0.356 8 5 6.20 4.00 6.00 3.90 2.29 5.80 3.80 0.457 1 4 FOR PROPER CONNECTION OF 1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO 3.81 REF THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW SECTION OF THIS DATA SHEET. 1.75 1.65 0.50 45° 1.35 1.25 0.25 0.25 0.17 0.10 MAX SEATING PLANE 0.05 NOM 8° 0.51 1.04 REF COPLANARITY 0° 1.27 0.31 0.10 0.40 -B 11 -20 2 COMPLIANT TO JEDEC STANDARDS MS-012-AA -0 06
Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters Rev. H | Page 22 of 23 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitance, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information ADIsimPower Design Tool Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programable Precision Enable Soft Start Noise Reduction of the ADP7142 in Adjustable Mode Effect of Noise Reduction on Start-Up Time Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide