Datasheet AD8564 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Quad 7 ns Single Supply Comparator |
| 页数 / 页 | 12 / 10 — AD8564. USING HYSTERESIS. COMPARATOR. SIGNAL. VREF |
| 修订版 | B |
| 文件格式/大小 | PDF / 275 Kb |
| 文件语言 | 英语 |
AD8564. USING HYSTERESIS. COMPARATOR. SIGNAL. VREF
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AD8564 USING HYSTERESIS
voltage is greater than VHI and does not switch low again until the input voltage is less than VLO, as given in Equation 2. Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator R1 V = V − − + 1 V V (1) HI ( REF ) REF offers an advantage in noisy environments where it is not desirable R1 + R2 for the output to toggle between states when the input signal is ⎛ ⎞ near the switching threshold. Figure 17 shows a method for V = ⎜ V 1 − R1 ⎟ (2) LO REF ⎜ ⎟ configuring the AD8564 with hysteresis. ⎝ R1 + R2 ⎠
COMPARATOR
where V+ is the positive supply voltage.
SIGNAL
The CF capacitor may also be added to introduce a pole into
R1 R2
the feedback network. This has the effect of increasing the
VREF
amount of hysteresis at high frequencies. This can be useful 17 0 3- when comparing a relatively slow signal in a high frequency
C
10
F
1 0 noise environment. Figure 17. Configuring the AD8564 with Hysteresis 1 The input signal is connected directly to the inverting input of At frequencies greater than f = , the hysteresis P 2 C π R2 the comparator. The output is fed back to the noninverting F input through R2 and R1. The ratio of R1 to R1 + R2 and the window approaches VHI = V+ – 1 V and VLO = 0 V. output swing establishes the width of the hysteresis window, At frequencies less than fP, the threshold voltages remain as it is with VREF setting the center of the window or the average in Equation 1. switching voltage. The output switches high when the input Rev. B | Page 10 of 12 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE OUTPUT LOADING CONSIDERATIONS INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS OUTLINE DIMENSIONS ORDERING GUIDE
AD8564 USING HYSTERESIS
voltage is greater than VHI and does not switch low again until the input voltage is less than VLO, as given in Equation 2. Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator R1 V = V − − + 1 V V (1) HI ( REF ) REF offers an advantage in noisy environments where it is not desirable R1 + R2 for the output to toggle between states when the input signal is ⎛ ⎞ near the switching threshold. Figure 17 shows a method for V = ⎜ V 1 − R1 ⎟ (2) LO REF ⎜ ⎟ configuring the AD8564 with hysteresis. ⎝ R1 + R2 ⎠
COMPARATOR
where V+ is the positive supply voltage.
SIGNAL
The CF capacitor may also be added to introduce a pole into
R1 R2
the feedback network. This has the effect of increasing the
VREF
amount of hysteresis at high frequencies. This can be useful 17 0 3- when comparing a relatively slow signal in a high frequency
C
10
F
1 0 noise environment. Figure 17. Configuring the AD8564 with Hysteresis 1 The input signal is connected directly to the inverting input of At frequencies greater than f = , the hysteresis P 2 C π R2 the comparator. The output is fed back to the noninverting F input through R2 and R1. The ratio of R1 to R1 + R2 and the window approaches VHI = V+ – 1 V and VLO = 0 V. output swing establishes the width of the hysteresis window, At frequencies less than fP, the threshold voltages remain as it is with VREF setting the center of the window or the average in Equation 1. switching voltage. The output switches high when the input Rev. B | Page 10 of 12 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE OUTPUT LOADING CONSIDERATIONS INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS OUTLINE DIMENSIONS ORDERING GUIDE