Datasheet ADCMP580, ADCMP581, ADCMP582 (Analog Devices) - 11

Data Sheet ADCMP580/ADCMP581/ADCMP582 TYPICAL APPLICATION CIRCUITS GND VTP 50Ω 50Ω VP ADCMP580 CML VP Q V V N IN VN ADCMP580 Q VTN 1k 50 Ω Ω 50Ω
021
VEE
04672-
LATCH
017
INPUTS
04672- Figure 16. Zero-Crossing Detector with CML Outputs on the ADCMP580 Figure 20. Disabling the Latch Feature on the ADCMP580
VTP VP Q V V P P V ADCMP581 RSECL N ADCMP581 V V N N Q VTN 50Ω 50Ω 50Ω 50Ω 750Ω VTT = –2V V VTT
022
TT VEE LATCH
018 04672-
INPUTS
04672- Figure 17. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver on the ADCMP581 Figure 21. Disabling the Latch Feature on the ADCMP581
VP ADCMP580 ADCMP582 RSPECL HYS VN 50 0 Ω 50Ω Ω TO 5kΩ 50Ω 750Ω 50Ω
019 023
VEE VCCO VTT = VCCO – 2V
04672- 04672- Figure 18. Adding Hysteresis Using the HYS Control on the ADCMP580 Figure 22. Disabling the Latch Feature on the ADCMP582
GND 50Ω 50Ω + Q VIN ADCMP580 VTH – Q LATCH INPUTS
020 04672- Figure 19. Comparator with −2 to +3 V Input Range on the ADCMP580 Rev. B | Page 11 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES