Datasheet ADN8834 (Analog Devices) - 16

ADN8834 Data Sheet
approach V
Using a Resistor Divider to Set the TEC Voltage Limit
B, the ramp slows down to avoid possible current overshoot at the point where the TEC voltage starts to build up. Separate voltage limits are set using a resistor divider. The
LDR
internal current sink circuitry connected to VLIM/SD draws a
REACH VOLTAGE LIMIT
current when the ADN8834 drives the TEC in a heating direction,
SFB
which lowers the voltage at VLIM/SD. The current sink is not
TEC VOLTAGE BUILDS UP
active when the TEC is driven in a cooling direction; therefore,
VB
the TEC heating voltage limit is always lower than the cooling voltage limit.
DISCHARGE SOFT START
023
PREBIAS BEGINS TIME
12954- Figure 30. Soft Start Profile in Cooling Mode
TEC VOLTAGE CLK LIMIT AND INTERNAL TEC VOLTAGE/CURRENT MONITOR SOFT START
The TEC real-time voltage and current are detectable at VTEC
HEATING V
and ITEC, respectively.
REF Voltage Monitor DISABLE RV1 10µA
VTEC is an analog voltage output pin with a voltage proportional
VLIM/SD
to the actual voltage across the TEC. A center VTEC voltage of 1.25 V corresponds to 0 V across the TEC. Convert the voltage
R SW OPEN = V V2 VLIMC SW CLOSED = V
at VTEC and the voltage across the TEC using the following
VLIMH
024 equation: 12954- Figure 31. Using a Resistor Divider to Set the TEC Voltage Limit VVTEC = 1.25 V + 0.25 × (VLDR − VSFB) Calculate the cooling and heating limits using the following
Current Monitor
equations: ITEC is an analog voltage output pin with a voltage proportional VVLIM_COOLING = VREF × RV2/(RV1 +RV2) to the actual current through the TEC. A center ITEC voltage of 1.25 V corresponds to 0 A through the TEC. Convert the where VREF = 2.5 V. voltage at ITEC and the current through the TEC using the VVLIM_HEATING = VVLIM_COOLING − ISINK_VLIM × RV1||RV2 following equations: where ISINK_VLIM = 10 µA. VITEC_COOLING = 1.25 V + ILDR × RCS VTEC_MAX_COOLING = VVLIM_COOLING × AVLIM where the current sense gain (RCS) is 0.525 V/A. where AVLIM = 2 V/V. VITEC_HEATING = 1.25 V − ILDR × RCS VTEC_MAX_HEATING = VVLIM_HEATING × AVLIM
MAXIMUM TEC VOLTAGE LIMIT
The maximum TEC voltage is set by applying a voltage divider at the VLIM/SD pin to protect the TEC. The voltage limiter operates bidirectional y and allows the cooling limit to be different from the heating limit. Rev. B | Page 16 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide