Datasheet AD9361 (Analog Devices) - 33

Data Sheet AD9361 THEORY OF OPERATION GENERAL
digital filter block is adjustable by changing decimation factors to produce the desired output data rate. The AD9361 is a highly integrated radio frequency (RF) transceiver capable of being configured for a wide range of
TRANSMITTER
applications. The device integrates all RF, mixed signal, and The transmitter section consists of two identical and independently digital blocks necessary to provide al transceiver functions in a controlled channels that provide all digital processing, mixed single device. Programmability allows this broadband transceiver signal, and RF blocks necessary to implement a direct conversion to be adapted for use with multiple communication standards, system while sharing a common frequency synthesizer. The digital including frequency division duplex (FDD) and time division data received from the BBP passes through a ful y programmable duplex (TDD) systems. This programmability also allows the 128-tap FIR filter with interpolation options. The FIR output is device to be interfaced to various baseband processors (BBPs) using sent to a series of interpolation filters that provide additional a single 12-bit parallel data port, dual 12-bit parallel data ports, filtering and data rate interpolation prior to reaching the DAC. or a 12-bit low voltage differential signaling (LVDS) interface. Each 12-bit DAC has an adjustable sampling rate. Both the I The AD9361 also provides self-calibration and automatic gain and Q channels are fed to the RF block for upconversion. control (AGC) systems to maintain a high performance level When converted to baseband analog signals, the I and Q signals are under varying temperatures and input signal conditions. In filtered to remove sampling artifacts and fed to the upconversion addition, the device includes several test modes that allow system mixers. At this point, the I and Q signals are recombined and designers to insert test tones and create internal loopback modes modulated on the carrier frequency for transmission to the that can be used by designers to debug their designs during output stage. The combined signal also passes through analog prototyping and optimize their radio configuration for a filters that provide additional band shaping, and then the signal specific application. is transmitted to the output amplifier. Each transmit channel
RECEIVER
provides a wide attenuation adjustment range with fine granularity to help designers optimize signal-to-noise ratio (SNR). The receiver section contains all blocks necessary to receive RF signals and convert them to digital data that is usable by a BBP. Self-calibration circuitry is built into each transmit channel to There are two independently control ed channels that can receive provide automatic real-time adjustment. The transmitter block signals from different sources, allowing the device to be used in also provides a TX monitor block for each channel. This block multiple input, multiple output (MIMO) systems while sharing monitors the transmitter output and routes it back through an a common frequency synthesizer. unused receiver channel to the BBP for signal monitoring. The TX monitor blocks are available only in TDD mode operation Each channel has three inputs that can be multiplexed to the while the receiver is idle. signal chain, making the AD9361 suitable for use in diversity systems with multiple antenna inputs. The receiver is a direct
CLOCK INPUT OPTIONS
conversion system that contains a low noise amplifier (LNA), The AD9361 operates using a reference clock that can be provided followed by matched in-phase (I) and quadrature (Q) amplifiers, by two different sources. The first option is to use a dedicated mixers, and band shaping filters that down convert received crystal with a frequency between 19 MHz and 50 MHz connected signals to baseband for digitization. External LNAs can also be between the XTALP and XTALN pins. The second option is to interfaced to the device, allowing designers the flexibility to connect an external oscil ator or clock distribution device (such as customize the receiver front end for their specific application. the AD9548) to the XTALN pin (with the XTALP pin remaining Gain control is achieved by fol owing a preprogrammed gain unconnected). If an external oscil ator is used, the frequency index map that distributes gain among the blocks for optimal can vary between 10 MHz and 80 MHz. This reference clock performance at each level. This can be achieved by enabling the is used to supply the synthesizer blocks that generate al data internal AGC in either fast or slow mode or by using manual clocks, sample clocks, and local oscillators inside the device. gain control, allowing the BBP to make the gain adjustments as Errors in the crystal frequency can be removed by using the needed. Additionally, each channel contains independent RSSI digitally programmable digitally controlled crystal oscillator measurement capability, dc offset tracking, and all circuitry (DCXO) function to adjust the on-chip variable capacitor. This necessary for self-calibration. capacitor can tune the crystal frequency variance out of the The receivers include 12-bit, Σ-Δ ADCs and adjustable sample system, resulting in a more accurate reference clock from which rates that produce data streams from the received signals. The all other frequency signals are generated. This function can also digitized signals can be conditioned further by a series of be used with on-chip temperature sensing to provide oscil ator decimation filters and a ful y programmable 128-tap FIR filter frequency temperature compensation during normal operation. with additional decimation settings. The sample rate of each Rev. F | Page 33 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE