Datasheet AD9361 (Analog Devices) - 12

AD9361 Data Sheet Table 8. FDD Mode, 800 MHz Parameter Min Typ Max Unit Test Conditions/Comments
1RX, 1TX 5 MHz Bandwidth 7 dBm 490 mA −27 dBm 345 mA 10 MHz Bandwidth 7 dBm 540 mA −27 dBm 395 mA 20 MHz Bandwidth 7 dBm 615 mA −27 dBm 470 mA 2RX, 1TX 5 MHz Bandwidth 7 dBm 555 mA −27 dBm 410 mA 10 MHz Bandwidth 7 dBm 625 mA −27 dBm 480 mA 20 MHz Bandwidth 7 dBm 740 mA −27 dBm 600 mA 1RX, 2TX 5 MHz Bandwidth 7 dBm 685 mA −27 dBm 395 mA 10 MHz Bandwidth 7 dBm 755 mA −27 dBm 465 mA 20 MHz Bandwidth 7 dBm 850 mA −27 dBm 570 mA 2RX, 2TX 5 MHz Bandwidth 7 dBm 790 mA −27 dBm 495 mA 10 MHz Bandwidth 7 dBm 885 mA −27 dBm 590 mA 20 MHz Bandwidth 7 dBm 1020 mA −27 dBm 730 mA Rev. F | Page 12 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE