Datasheet AD9363 (Analog Devices) - 29

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Data Sheet AD9363 BB PLL ENABLE STATE MACHINE
The AD9363 also contains a baseband PLL (BB PLL) synthesizer The AD9363 transceiver includes an ENSM that al ows real- that generates all baseband related clock signals. These signals time control over the current state of the device. The device can include the ADC and DAC sampling clocks, the DATA_CLK signal be placed in several different states during normal operation, (see the Digital Data Interface section), and al data framing including signals. The BB PLL is programmed from 700 MHz to 1400 MHz • based on the data rate and sample rate requirements of the system. Wait—power save, synthesizers disabled • Sleep—wait with all clocks and the BB PLL disabled
DIGITAL DATA INTERFACE
• Tx—Tx signal chain enabled The AD9363 data interface uses paral el data ports (P0 and P1) • Rx—Rx signal chain enabled to transfer data between the device and the BBP. The data ports • FDD—Tx and Rx signal chains enabled can be configured in either single-ended CMOS format or dif- • Alert—synthesizers enabled ferential LVDS format. Both formats can be configured in multiple arrangements to match system requirements for data ordering The ENSM has two control modes: SPI control and pin control. and data port connections. These arrangements include single
SPI Control Mode
port data bus, dual port data bus, single data rate, double data In SPI control mode, the ENSM is controlled asynchronously by rate, and various combinations of data ordering to transmit data writing to SPI registers to advance the current state to the next from different channels across the bus at appropriate times. state. SPI control is considered asynchronous to the DATA_CLK Bus transfers are controlled using simple hardware handshake signal because the SPI clock can be derived from a different signaling. The two ports can be operated in either bidirectional clock reference and can still function properly. The SPI control (TDD) mode or in full duplex (FDD) mode, where half the bits ENSM mode is recommended when real-time control of the are used for transmitting data and half are used for receiving synthesizers is not necessary. SPI control can be used for real- data. The interface can also be configured to use only one of the time control as long as the BBP can perform timed SPI writes data ports for applications that do not require high data rates accurately. and require fewer interface pins.
Pin Control Mode DATA_CLK Signal
In pin control mode, the enable functions of the ENABLE pin The AD9363 outputs the DATA_CLK signal that the BBP uses and the TXNRX pin allow real-time control of the current state. to sample receiver data. The signal is synchronized with the The ENSM al ows TDD or FDD operation, depending on the receiver data such that data transitions occur out of phase with configuration of the corresponding SPI register. The ENABLE DATA_CLK. The DATA_CLK can be set to a rate that provides and TXNRX pin control mode is recommended if the BBP has single data rate (SDR) timing, where data is sampled on each rising extra control outputs that can be control ed in real time, al ow- clock edge, or it can be set to provide double data rate (DDR) ing a simple 2-wire interface to control the state of the device. timing, where data is captured on both rising and fal ing clock To advance the current state of the ENSM to the next state, edges. SDR or DDR timing applies to operation using either a drive the enable function of the ENABLE pin by either a pulse single port or both ports. (edge detected internal y) or a level.
FB_CLK Signal
When a pulse is used, it must have a minimum pulse width of For transmit data, the interface uses the FB_CLK signal as the one cycle of the FB_CLK signal. In level mode, the ENABLE timing reference. The FB_CLK signal al ows source synchro- and TXNRX pins are also edge detected by the AD9363 and nous timing with rising edge capture for burst control signals must meet the same minimum pulse width requirement of one and either rising edge capture (SDR mode) or both edge capture cycle of the FB_CLK signal. (DDR mode) for transmit signal bursts. The FB_CLK signal In FDD mode, the ENABLE and TXNRX pins can be remapped must have the same frequency and duty cycle as DATA_CLK. to serve as real-time Rx and Tx data transfer control signals. In
RX_FRAME and TX_FRAME Signals
this mode, the ENABLE pin assumes the receive on (RXON) function (controls when the Rx path is enabled and disabled), and The device generates an RX_FRAME output signal whenever the TXNRX pin assumes the transmit on (TXON) function the receiver outputs valid data. This signal has two modes: level (controls when the Tx path is enabled and disabled). The ENSM mode (the RX_FRAME signal stays high as long as the data is must be control ed by SPI writes in this mode while the ENABLE valid) and pulse mode (the RX_FRAME signal pulses with a 50% and TXNRX pins control all data flow. For more information duty cycle). Similarly, the BBP must provide a TX_FRAME about RXON and TXON, see the AD9363 reference manual, signal that indicates the beginning of a valid data transmission available from Integrated Wideband RF Transceiver Design with a rising edge. Like the RX_FRAME signal, the TX_FRAME Resources. signal stays high throughout the burst or it pulses with a 50% duty cycle. Rev. D | Page 29 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE