AD9363Data SheetTYPICAL PERFORMANCE CHARACTERISTICS ATTEN is the attenuation setting. fLO_RX and fLO_TX are the receive and transmit local oscillator frequencies, respectively. 800 MHZ FREQUENCY BAND4.00–40°C–40°C+25°C3.5+25°C+85°C+85°C3.0–4B) d ( 2.5) BURE IG 2.0–8F EEVM (dISx R1.5Rx NO1.0–120.50–16700750800850900 003 –56–54–52–50–48–46–44–42–40–38–36 007 RF FREQUENCY (MHz)INTERFERER POWER LEVEL (dBm) 10558- 10558- Figure 3. Rx Noise Figure vs. RF Frequency Figure 6. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset 514–40°C–40°C+25°C+25°C4+85°C+85°C123B) 10B)dd2(R (URE81IGRROFI EES6IS0RSRx NO4–1–22–30–100–90–80–70–60–50–40–30–20–10 004 –47–43–39–35–31–27–23 008 Rx INPUT POWER (dBm) 10558- INTERFERER POWER LEVEL (dBm) 10558- Figure 4. RSSI Error vs. Rx Input Power, LTE 10 MHz Modulation Figure 7. Rx Noise Figure vs. Interferer Power Level, Enhanced Data Rates for (Referenced to −50 dBm Input Power at 800 MHz) GSM Evolution (EDGE) Signal of Interest with PIN = −90 dBm, Continuous Wave (CW) Blocker at 3 MHz Offset, Gain Index = 64 080–40°C–40°C+25°C+25°C+85°C+85°C–57876–10) BB) d74–15N ( AIEVM (d x72RRx G–2070–2568–3066–72–68–64–60–56–52–48–44–40–36–32 006 700750800850900 009 INTERFERER POWER LEVEL (dBm) 10558- Rx LO FREQUENCY (MHz) 10558- Figure 5. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest Figure 8. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting) with PIN = −82 dBm, 5 MHz Orthogonal Frequency Division Multiplexing (OFDM) Blocker at 7.5 MHz Offset Rev. D | Page 20 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE