Datasheet AD9364 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | RF Agile Transceiver |
| 页数 / 页 | 32 / 8 — AD9364. Data Sheet. CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx … |
| 修订版 | C |
| 文件格式/大小 | PDF / 592 Kb |
| 文件语言 | 英语 |
AD9364. Data Sheet. CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES)
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AD9364 Data Sheet CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) Table 5. 800 MHz, TDD Mode Parameter Min Typ Max Unit Test Conditions/Comments
RX 5 MHz Bandwidth 180 mA Continuous Rx 10 MHz Bandwidth 210 mA Continuous Rx 20 MHz Bandwidth 260 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 340 mA Continuous Tx −27 dBm 190 mA Continuous Tx 10 MHz Bandwidth 7 dBm 360 mA Continuous Tx −27 dBm 220 mA Continuous Tx 20 MHz Bandwidth 7 dBm 400 mA Continuous Tx −27 dBm 250 mA Continuous Tx
Table 6. TDD Mode, 2.4 GHz Parameter Min Typ Max Unit Test Conditions/Comments
RX 5 MHz Bandwidth 175 mA Continuous Rx 10 MHz Bandwidth 200 mA Continuous Rx 20 MHz Bandwidth 240 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 350 mA Continuous Tx −27 dBm 160 mA Continuous Tx 10 MHz Bandwidth 7 dBm 380 mA Continuous Tx −27 dBm 220 mA Continuous Tx 20 MHz Bandwidth 7 dBm 410 mA Continuous Tx −27 dBm 260 mA Continuous Tx
Table 7. TDD Mode, 5.5 GHz Parameter Min Typ Max Unit Test Conditions/Comments
RX 5 MHz Bandwidth 175 mA Continuous Rx 40 MHz Bandwidth 275 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 400 mA Continuous Tx −27 dBm 240 mA Continuous Tx 40 MHz Bandwidth 7 dBm 490 mA Continuous Tx −27 dBm 385 mA Continuous Tx Rev. C | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide
RX 5 MHz Bandwidth 180 mA Continuous Rx 10 MHz Bandwidth 210 mA Continuous Rx 20 MHz Bandwidth 260 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 340 mA Continuous Tx −27 dBm 190 mA Continuous Tx 10 MHz Bandwidth 7 dBm 360 mA Continuous Tx −27 dBm 220 mA Continuous Tx 20 MHz Bandwidth 7 dBm 400 mA Continuous Tx −27 dBm 250 mA Continuous Tx
Table 6. TDD Mode, 2.4 GHz Parameter Min Typ Max Unit Test Conditions/Comments
RX 5 MHz Bandwidth 175 mA Continuous Rx 10 MHz Bandwidth 200 mA Continuous Rx 20 MHz Bandwidth 240 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 350 mA Continuous Tx −27 dBm 160 mA Continuous Tx 10 MHz Bandwidth 7 dBm 380 mA Continuous Tx −27 dBm 220 mA Continuous Tx 20 MHz Bandwidth 7 dBm 410 mA Continuous Tx −27 dBm 260 mA Continuous Tx
Table 7. TDD Mode, 5.5 GHz Parameter Min Typ Max Unit Test Conditions/Comments
RX 5 MHz Bandwidth 175 mA Continuous Rx 40 MHz Bandwidth 275 mA Continuous Rx TX 5 MHz Bandwidth 7 dBm 400 mA Continuous Tx −27 dBm 240 mA Continuous Tx 40 MHz Bandwidth 7 dBm 490 mA Continuous Tx −27 dBm 385 mA Continuous Tx Rev. C | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide