Datasheet ADRV9008-2 (Analog Devices)

制造商Analog Devices
描述Integrated Dual RF Transmitter and Observation Receiver
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Integrated Dual RF Transmitters and. Observation Receiver. Data Sheet. ADRV9008-2. FEATURES. Dual transmitters

Datasheet ADRV9008-2 Analog Devices

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Integrated Dual RF Transmitters and Observation Receiver Data Sheet ADRV9008-2 FEATURES
global system for mobile communications (MC GSM) mode,
Dual transmitters
which has higher inband spurious-free dynamic range (SFDR),
Dual input shared observation receiver
the maximum large signal bandwidth is 75 MHz.
Maximum tunable transmitter synthesis bandwidth: 450 MHz
The observation path consists of a wide bandwidth direct
Maximum observation receiver bandwidth: 450 MHz
conversion receiver with state of the art dynamic range. The
Fully integrated fractional-N RF synthesizers
complete receive subsystem includes dc offset correction,
Fully integrated clock synthesizer
quadrature correction, and digital filtering, thus eliminating the
Multichip phase synchronization for RF LO and baseband
need for these functions in the digital baseband. Several
clocks
auxiliary functions such as analog-to-digital converters (ADCs),
JESD204B datapath interface
digital-to-analog converters (DACs), and general-purpose
Tuning range (center frequency): 75 MHz to 6000 MHz
inputs/outputs (GPIOs) for power amplifier (PA) and radio
APPLICATIONS
frequency (RF) front-end control are also integrated.
2G/3G/4G/5G macrocell base stations
The fully integrated phase-locked loops (PLLs) provide high
Active antenna systems
performance, low power fractional-N RF frequency synthesis for
Massive multiple input, multiple output (MIMO)
the transmitter and receiver sections. An additional synthesizer
Phased array radars
generates the clocks needed for the converters, digital circuits, and
Electronic warfare
the serial interface. Special precautions have been taken to
Military communications
provide the isolation required in high performance base station
Portable test equipment
applications. Al voltage controlled oscil ators (VCOs) and loop
GENERAL DESCRIPTION
filter components are integrated. The ADRV9008-2 is a highly integrated, RF agile transmit The high speed JESD204B interface supports up to 12.288 Gbps subsystem offering dual-channel transmitters, an observation path lane rates, resulting in two lanes per transmitter in the widest receiver, integrated synthesizers, and digital signal processing bandwidth mode and two lanes for the observation path functions. The IC delivers a versatile combination of high receiver in the widest bandwidth mode. performance and low power consumption required by The core of the ADRV9008-2 can be powered directly from 2G/3G/4G/5G macrocell base stations, and active antenna 1.3 V regulators and 1.8 V regulators and is controlled via a applications. standard 4-wire serial port. Comprehensive power-down modes The transmitters use an innovative direct conversion modulator are included to minimize power consumption in normal use. that achieves multicarrier macrocell base station quality The ADRV9008-2 is packaged in a 12 mm × 12 mm 196-ball performance and low power. In 3G/4G mode, the maximum chip scale ball grid array (CSP_BGA). transmitter large signal bandwidth is 200 MHz. In multicarrier
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide