Datasheet ADRV9026 (Analog Devices) - 116
| 制造商 | Analog Devices |
| 描述 | Integrated, Quad RF Transceiver with Observation Path |
| 页数 / 页 | 118 / 116 — ADRV9026. Data Sheet. JTAG BOUNDARY SCAN. Table 15. Dual Function … |
| 修订版 | A |
| 文件格式/大小 | PDF / 2.8 Mb |
| 文件语言 | 英语 |
ADRV9026. Data Sheet. JTAG BOUNDARY SCAN. Table 15. Dual Function Boundary Scan Test Pins. Mnemonic. JTAG Mnemonic. Description
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ADRV9026 Data Sheet JTAG BOUNDARY SCAN Table 15. Dual Function Boundary Scan Test Pins
The ADRV9026 provides support for a JTAG boundary scan.
Mnemonic JTAG Mnemonic Description
There are five dual function pins associated with the JTAG GPIO_14 E TR ST Test access port reset interface. These pins, listed in Table 15, are used to access the GPIO_15 TDO Test data output on-chip test access port. To enable the JTAG functionality, set GPIO_16 TDI Test data input the GPIO_0 pin through the GPIO_2 pin according to Table 16, GPIO_17 TMS Test access port mode select depending on how the desired JESD204B sync signals are GPIO_18 TCK Test clock configured in the software (differential or single-ended mode). Pul the TEST_EN pin high to the VIF supply to enable the JTAG
Table 16. JTAG Modes
mode.
Test Pin Level GPIO_2 to GPIO_0 Description
0 XXX1 Normal operation 1 000 JTAG mode with differential JESD204B sync signals 1 011 JTAG mode with single- ended JESD204B sync signals 1 X means any combination. Rev. A | Page 116 of 118 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide
ADRV9026 Data Sheet JTAG BOUNDARY SCAN Table 15. Dual Function Boundary Scan Test Pins
The ADRV9026 provides support for a JTAG boundary scan.
Mnemonic JTAG Mnemonic Description
There are five dual function pins associated with the JTAG GPIO_14 E TR ST Test access port reset interface. These pins, listed in Table 15, are used to access the GPIO_15 TDO Test data output on-chip test access port. To enable the JTAG functionality, set GPIO_16 TDI Test data input the GPIO_0 pin through the GPIO_2 pin according to Table 16, GPIO_17 TMS Test access port mode select depending on how the desired JESD204B sync signals are GPIO_18 TCK Test clock configured in the software (differential or single-ended mode). Pul the TEST_EN pin high to the VIF supply to enable the JTAG
Table 16. JTAG Modes
mode.
Test Pin Level GPIO_2 to GPIO_0 Description
0 XXX1 Normal operation 1 000 JTAG mode with differential JESD204B sync signals 1 011 JTAG mode with single- ended JESD204B sync signals 1 X means any combination. Rev. A | Page 116 of 118 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide