Datasheet AD8363 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 50 Hz to 6 GHz 50 dB TruPwr Detector |
| 页数 / 页 | 29 / 2 — AD8363. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 3/15—Rev. A to … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
AD8363. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 3/15—Rev. A to Rev. B. 7/11—Rev. 0 to Rev. A
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AD8363 Data Sheet TABLE OF CONTENTS
Features .. 1 VSET Interface .. 17 Applications ... 1 Output Interface ... 17 Functional Block Diagram .. 1 VTGT Interface .. 18 General Description ... 1 Measurement Mode Basic Connections.. 18 Revision History ... 2 System Calibration and Error Calculation .. 19 Specifications ... 3 Operation to 125°C .. 19 Absolute Maximum Ratings .. 7 Output Voltage Scaling .. 20 ESD Caution .. 7 Offset Compensation, Minimum CLPF, and Maximum CHPF Pin Configuration and Function Descriptions ... 8 Capacitance Values ... 20 Typical Performance Characteristics ... 9 Choosing a Value for CLPF .. 21 Theory of Operation .. 14 RF Pulse Response and VTGT ... 23 Square Law Detector and Amplitude Target .. 14 Controller Mode Basic Connections ... 23 RF Input Interface .. 15 Constant Output Power Operation .. 24 Choice of RF Input Pin .. 15 Description of RF Characterization ... 25 Small Signal Loop Response ... 15 Evaluation and Characterization Circuit Board Layouts .. 26 Temperature Sensor Interface ... 16 Assembly Drawings .. 28 VREF Interface ... 16 Outline Dimensions ... 29 Temperature Compensation Interface ... 16 Ordering Guide .. 29 Power-Down Interface ... 17
REVISION HISTORY 3/15—Rev. A to Rev. B
Changes to Figure 2 and Table 3 ... 8 Changes to Controller Mode Basic Connections Section ... 23 Updated Outline Dimensions ... 29 Changes to the Ordering Guide .. 29
7/11—Rev. 0 to Rev. A
Changes to Features Section and Applications Section ... 1 Added 3-Point Calibration to Table 1 for All MHz .. 3 Replaced Typical Performance Characteristics Section; Renumbered Sequentially .. 9 Changes to Theory of Operation Section .. 14 Changes to Temperature Compensation Interface Section .. 16 Changes to System Calibration and Error Calculation Section and Changes to Figure 44 and Figure 45 ... 19 Deleted Basis for Error Calculations Section .. 20 Changes to Figure 46 .. 20 Deleted Selecting and Increasing Calibration Points to Improve Accuracy over a Reduced Range Section ... 22 Deleted Altering the Slope Section .. 23 Added Output Voltage Scaling Section ... 23
5/09—Revision 0: Initial Version
Rev. B | Page 2 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE
AD8363 Data Sheet TABLE OF CONTENTS
Features .. 1 VSET Interface .. 17 Applications ... 1 Output Interface ... 17 Functional Block Diagram .. 1 VTGT Interface .. 18 General Description ... 1 Measurement Mode Basic Connections.. 18 Revision History ... 2 System Calibration and Error Calculation .. 19 Specifications ... 3 Operation to 125°C .. 19 Absolute Maximum Ratings .. 7 Output Voltage Scaling .. 20 ESD Caution .. 7 Offset Compensation, Minimum CLPF, and Maximum CHPF Pin Configuration and Function Descriptions ... 8 Capacitance Values ... 20 Typical Performance Characteristics ... 9 Choosing a Value for CLPF .. 21 Theory of Operation .. 14 RF Pulse Response and VTGT ... 23 Square Law Detector and Amplitude Target .. 14 Controller Mode Basic Connections ... 23 RF Input Interface .. 15 Constant Output Power Operation .. 24 Choice of RF Input Pin .. 15 Description of RF Characterization ... 25 Small Signal Loop Response ... 15 Evaluation and Characterization Circuit Board Layouts .. 26 Temperature Sensor Interface ... 16 Assembly Drawings .. 28 VREF Interface ... 16 Outline Dimensions ... 29 Temperature Compensation Interface ... 16 Ordering Guide .. 29 Power-Down Interface ... 17
REVISION HISTORY 3/15—Rev. A to Rev. B
Changes to Figure 2 and Table 3 ... 8 Changes to Controller Mode Basic Connections Section ... 23 Updated Outline Dimensions ... 29 Changes to the Ordering Guide .. 29
7/11—Rev. 0 to Rev. A
Changes to Features Section and Applications Section ... 1 Added 3-Point Calibration to Table 1 for All MHz .. 3 Replaced Typical Performance Characteristics Section; Renumbered Sequentially .. 9 Changes to Theory of Operation Section .. 14 Changes to Temperature Compensation Interface Section .. 16 Changes to System Calibration and Error Calculation Section and Changes to Figure 44 and Figure 45 ... 19 Deleted Basis for Error Calculations Section .. 20 Changes to Figure 46 .. 20 Deleted Selecting and Increasing Calibration Points to Improve Accuracy over a Reduced Range Section ... 22 Deleted Altering the Slope Section .. 23 Added Output Voltage Scaling Section ... 23
5/09—Revision 0: Initial Version
Rev. B | Page 2 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE