Data SheetADL5902ASSEMBLY DRAWINGS 60 0 061 8- 8- 21 08 0821 Figure 55. Evaluation Board Layout, Top Side Figure 56. Evaluation Board Layout, Bottom Side Rev. B | Page 27 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE BASIS FOR ERROR CALCULATIONS MEASUREMENT MODE BASIC CONNECTIONS SETTING VTADJ SETTING VTGT CHOOSING A VALUE FOR CLPF OUTPUT VOLTAGE SCALING SYSTEM CALIBRATION AND ERROR CALCULATION HIGH FREQUENCY PERFORMANCE LOW FREQUENCY PERFORMANCE DESCRIPTION OF CHARACTERIZATION EVALUATION BOARD SCHEMATICS AND ARTWORK ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE