Datasheet ADUCM355 (Analog Devices) - 15

link to page 24 link to page 24 link to page 15 link to page 15 link to page 15
Data Sheet ADuCM355 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Impedance Spectroscopy Mode1 11.5 mA When ac impedance engine (80 kHz) and ADC are active in low power mode, Arm processor also active with 26 MHz clock (TA = −40°C to +60°C) 21 mA When ac impedance engine (200 kHz) and ADC are active in high power mode, Arm processor also active with 26 MHz clock (TA = −40°C to +60°C) 1 Guaranteed by design, but not production tested. 2 If the ADC is calibrated to the recommended target of 1.835 V, the calculation for LSB size becomes (1.835 V/215)/PGA gain. 3 Code distribution can be reduced if the ADC output rate is reduced by using the sinc2 filter option. 4 ADC offset and gain are not calibrated for high power mode during production. User calibration can eliminate this error. 5 Noise can be reduced if the ADC output rate is reduced by using the sinc2 filter option. 6 Measured using the box method. 7 See Figure 10 for more details. 8 The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period. 9 See Figure 8 for more details. 10 DAC linearity is calculated using a reduced code range of 0x10 (lower limit) to 0xF40 (upper limit). 11 The average current from all GPIO pins must not exceed 20 mA per pin. 12 High speed DAC offset calibration can remove this error. See the ADuCM355 Hardware Reference Manual for more details. 13 It is recommended that the user enable power supply monitoring features to ensure operation, only when DVDD and AVDD are above 2.8 V. 14 DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V voltage reference. 15 Power figures exclude load currents from external circuits.
RMS NOISE RESOLUTION OF ADC
The rms noise specifications for the ADC with different ADC digital filter settings are described in Table 2. The internal 1.82 V reference was used for all measurements. Table 3 shows the rms and peak-to-peak effective bits based on the noise results in Table 2 for various PGA gain settings. Peak-to-peak effective bits results are shown in parentheses. RMS bits are calculated as follows:  2 Input Range  log 2    RMS Noise  Peak-to-peak bits are calculated as follows:  2 Input Range  log 2    6.6 RMS Noise 
Table 2. ADC RMS Noise RMS Noise (μV) Update Rate (Hz) Sinc3 Oversampling Rate (OSR) Sinc2 OSR Gain = 1 Gain = 1.5 Gain = 2 Gain = 4 Gain = 9
200000 4 Not applicable 72.43 49.732 37.83 18.93 8.62 9090 4 22 29.29 19.59 10.4 6.687 4.42 900 5 178 24.0 17.11 12.832 6.416 1.018
Table 3. ADC Effective Bits, Based on RMS Noise Settling Time Settling Time (50 Hz and (50 Hz and Update Sinc3 60 Hz Filter 60 Hz Filter Rate (Hz) OSR Sinc2 OSR Gain = 1 Gain = 1.5 Gain = 2 Gain = 4 Gain = 9 Disabled) Enabled)
200000 4 Not 14.6 15 14.95 14.95 14.9 16.25 μs 16.25 μs applicable (11.9 p-p) (12.4 p-p) (12.23 p-p) (12.23 p-p) (12.15 p-p) 9090 4 22 15 15 15 15 15 236.25 μs 236.25 μs (13.18 p-p) (13.8 p-p) (14.09 p-p) (13.73 p-p) (13.15 p-p) 900 5 178 15 15 15 15 15 2.245 ms 37 ms (13.47 p-p) (13.96 p-p) (13.8 p-p) (13.79 p-p) (15 p-p) Rev. C | Page 15 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE