Datasheet AD7294 (Analog Devices) - 3

Data Sheet AD7294 REVISION HISTORY 2/16—Rev. H to Rev. I
Changes to Table 2 .. 6 Changed CP-56-1 to CP-56-11 .. Throughout Changes to Table 6 .. 10 Changes to Figure 4 ... 11 Added Figure 4 .. 11 Updated Outline Dimensions .. 46 Changes to Table 7 .. 12 Changes to Ordering Guide ... 46 Changes to Command Register Section .. 28

Changes to Autocycle Mode Section .. 40
1/12—Rev. G to Rev. H
Updated Outline Dimensions .. 47 Changes to Table 2 .. 6 Changes to Ordering Guide ... 48
11/11—Rev. F to Rev. G 7/09—Rev. B to Rev. C
Change to DAC Output Characteristics Parameter of Changes to Table 4 Endnotes ... 8 Table 1 ... 5 Deleted DAC HIGH-Z Pin Leakage from Table 3 .. 8
4/09—Rev. A to Rev. B
Change to Figure 4 .. 11 Changes to Table 2 .. 6 Changes to Table 7 .. 12 Changes to Table 3 .. 7 Deleted Figure 47; Renumbered Sequentially ... 25 Changes to Table 23 .. 29 Deleted High Impedance Input Pin Section .. 26
3/09—Rev. 0 to Rev. A 11/10—Rev. E to Rev. F
Changes to Configuration Register (0x09) Section .. 29 Change to Table 2, Dynamic Performance, Spurious-Free Changes to Table 23 and Table 24 ... 29 Dynamic Range (SFDR) ... 6 Changes to Table 27 .. 30 Changes to Autocycle Mode Section .. 38
10/10—Rev. D to Rev. E
Change to Alert Status Registers Section ... 39 Change to Reflow Temperature, Table 5 .. 10 Changes to DATAHIGH and DATALOW Monitoring Features

Section .. 39
5/10—Rev. C to Rev. D
Added 56-Lead LFCSP .. Universal
1/08—Revision 0: Initial Version
Change to Features Section and General Description Section ... 1 Rev. I | Page 3 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DAC SPECIFICATIONS ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS I2C Serial Interface Timing and Circuit Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY DAC TERMINOLOGY ADC TERMINOLOGY THEORY OF OPERATION ADC OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode CURRENT SENSOR Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection ANALOG COMPARATOR LOOP TEMPERATURE SENSOR Remote Sensing Diode Ideality Factor Base Emitter Voltage Base Resistance hFE Variation Series Resistance Cancellation DAC OPERATION Resistor String Output Amplifier ADC AND DAC REFERENCE VDRIVE FEATURE REGISTER SETTING ADDRESS POINTER REGISTER COMMAND REGISTER (0x00) RESULT REGISTER (0x01) ADC Channel Allocation TSENSE1, TSENSE2 RESULT REGISTERS (0X02 AND 0X03) TSENSEINT RESULT REGISTER (0X04) Temperature Value Format DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04) ALERT STATUS REGISTER A (0x05), REGISTER B (0x06), AND REGISTER C (0x07) CHANNEL SEQUENCE REGISTER (0x08) CONFIGURATION REGISTER (0x09) Sample Delay and Bit Trial Delay POWER-DOWN REGISTER (0x0A) DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) HYSTERESIS REGISTERS: 0X0D (VIN0), 0X10 (VIN1), 0X13 (VIN2), 0X16 (VIN3) TSENSE OFFSET REGISTERS (0x26 AND 0x27) I2C INTERFACE GENERAL I2C TIMING SERIAL BUS ADDRESS BYTE INTERFACE PROTOCOL Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register MODES OF OPERATION COMMAND MODE AUTOCYCLE MODE ALERTS AND LIMITS THEORY ALERT_FLAG BIT ALERT STATUS REGISTERS DATAHIGH AND DATALOW MONITORING FEATURES HYSTERESIS Using the Limit Registers to Store Minimum/Maximum Conversion Results APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER MONITOR AND CONTROL GAIN CONTROL OF POWER AMPLIFIER LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING Layout Considerations for External Temperature Sensors OUTLINE DIMENSIONS ORDERING GUIDE