Datasheet ADAS1000, ADAS1000-1, ADAS1000-2 (Analog Devices) - 80

ADAS1000/ ADAS1000-1 /ADAS1000-2 Data Sheet Example 4: Configure 150 Hz Test Tone Sine Wave on Example 5: Enable Pace Detection and Stream Each ECG Channel and Stream Conversion Data Conversion Data
1. Write 1 configures the CMREFCTL register to 1. Write 1 configures the PACECTL register with all three VCM_REF = 1.3 V (no electrodes contribute to VCM). pace detection instances enabled, PACE1EN detecting on RLD is enabled to RLD_OUT, and the shield amplifier Lead II, PACE2EN detecting on Lead I, and PACE3EN enabled. detecting on Lead aVF. The pace width filter and validation 2. Write 2 addresses the TESTTONE register to enable the filters are also enabled. 150 Hz sine wave onto all electrode channels. 2. Write 2 issues the read command to start putting the 3. Write 3 addresses the FILTCTL register to change the internal converted data out on the SDO pin. low-pass filter to 250 Hz to ensure that the 150 Hz sine 3. Continue to issue SCLK cycles to read the converted data wave can pass through. at the configured packet data rate. When a valid pace is 4. Write 4 configures the FRMCTL register to output nine words detected, the detection flags are confirmed in the header per frame/packet. The frame/packet of words consists of the word and the PACEDATA register contains information header and five ECG words, pace, respiration magnitude, on the width and height of the measured pulse from each and lead-off. The frame is configured to always send, measured lead. irrespective of ready status. The ADAS1000 is in electrode 4. Note that the PACEAMPTH register default setting is format mode with a data rate of 2 kHz. Electrode format is 0x242424, setting the amplitude of each of the pace required to see the test tone signal correctly on each instances to 1.98 mV/gain. electrode channel. 5. Note that this example assumes that the FRMCTL register 5. Write 5 addresses the ECGCTL register, enabling all has already been configured such that the PACEDATA channels into a gain of 1.4, low noise mode. It configures word is available in the data frame, as arranged in Write 2 the device as a master and driven from the XTAL input of Example 1. source. The ADAS1000 is also put into conversion mode in this write. 6. Write 6 issues the read command to start putting the converted data out on the SDO pin. 7. Continue to issue SCLK cycles to read the converted data at the configured packet data rate.
Table 59. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 CMREFCTL 1 000 0101 0000 0000 0000 0000 0000 1011 0x8500000B Write 2 TESTTONE 1 000 1000 1111 1000 0000 0000 0000 1101 0x88F8000D Write 3 FILTCTL 1 000 1011 0000 0000 0000 0000 0000 1000 0x8B000008 Write 4 FRMCTL 1 000 1010 0000 0111 1001 0110 0001 0000 0x8A079610 Write 5 ECGCTL 1 000 0001 1111 1000 0000 0000 1010 1110 0x81F800AE Write 6 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000
Table 60. Example 5: Enable Pace Detection and Stream Conversion Data Write Command Register Addressed Read/Write Bit Register Address Data 32-Bit Write Command
Write 1 PACECTL 1 000 0100 0000 0000 0000 1111 1000 1111 0x84000F8F Write 2 FRAMES 0 100 0000 0000 0000 0000 0000 0000 0000 0x40000000 Rev. C | Page 80 of 85 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Noise Performance Timing Characteristics Standard Serial Interface Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ADAS1000-1 Only Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Applications Information Overview ECG Inputs—Electrodes/Leads ECG Channel Electrode/Lead Formation and Input Stage Configuration Analog Lead Mode and Calculation Digital Lead Mode and Calculation Electrode Mode: Single-Ended Input Electrode Configuration Electrode Mode: Common Electrode A and Electrode B Configurations Defibrillator Protection ESIS Filtering ECG Path Input Multiplexing Common-Mode Selection and Averaging Wilson Central Terminal (WCT) Right Leg Drive/Reference Drive Calibration DAC Gain Calibration Lead-Off Detection DC Lead-Off Detection DC Lead-Off and High Gains DC Lead-Off Debounce Timer AC Lead-Off Detection ACLO and Common-Mode Configuration ADC Out of Range Shield Driver Respiration (ADAS1000 Model Only) Internal Respiration Capacitors External Respiration Path External Respiration Capacitors Respiration Carrier Frequency Evaluating Respiration Performance Extend Switch On Respiration Paths Pacing Artifact Detection Function (ADAS1000 Only) Choice of Leads Detection Algorithm Overview Pace Edge Threshold Pace Level Threshold Pace Amplitude Threshold Pace Validation Filters Pace Width Filter Biventricular Pacers Pace Detection Measurements Evaluating Pace Detection Performance Pace Width Pace Latency Pace Detection via Secondary Serial Interface (ADAS1000 and ADAS1000-1 Only) Filtering Voltage Reference Gang Mode Operation Master/Slave Synchronizing Devices Calibration Common Mode Right Leg Drive Sequencing Devices into Gang Mode Number of Devices in Gang Mode Interfacing in Gang Mode Serial Interfaces Standard Serial Interface Write Mode Write/Read Data Format Data Frames/Packets Read Mode Serial Clock Rate Data Rate and Skip Mode Data Ready (DRDYB) Detecting Missed Conversion Data SPI Interface Resync CRC Word Clocks Secondary Serial Interface RESETB PDB Function SPI Output Frame Structure (ECG and Status Data) SPI Register Definitions and Memory Map Control Registers Details Examples of Interfacing to the ADAS1000 Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data Example 2: Enable Respiration and Stream Conversion Data Example 3: DC Lead-Off and Stream Conversion Data Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Slave Configuration Master Configuration Software Flowchart Power Supply, Grounding, and Decoupling Strategy AVDD ADCVDD and DVDD Supplies Unused Pins/Paths Layout Recommendations Outline Dimensions Ordering Guide