Datasheet KSZ8852HLE (Microchip) - 6

KSZ8852HLE MDI-X - Medium Dependent Interface
An Ethernet port connection that allows networked end stations (i.e.,
Crossover
PCs or workstations) to connect to each other using a null-modem, or crossover, cable. For 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter con- nects to the far end receiver. When connecting two computers together, a cable that crosses the TX and RX is required to do this. With auto MDI-X, the PHY senses the correct TX and RX roles, elim- inating any cable confusion.
MIB - Management Information Base
The MIB comprises the management portion of network devices. This can include things like monitoring traffic levels and faults (statis- tical), and can also change operating parameters in network nodes (static forwarding addresses).
MII - Media Independent Interface
The MII accesses PHY registers as defined in the IEEE 802.3 speci- fication.
NIC - Network Interface Card
An expansion board inserted into a computer to allow it to be con- nected to a network. Most NICs are designed for a particular type of network, protocol, and media, although some can serve multiple net- works.
NPVID - Non Port VLAN ID
The Port VLAN ID value is used as a VLAN reference.
PLL - Phase-Locked Loop
An electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or ref- erence, signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency.
QMU - Queue Management Unit
Manages packet traffic between MAC/PHY interface and the system host. The QMU has built-in packet memories for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue).
SA - Source Address
The address from which information has been sent.
TDR - Time Domain Reflectometry
TDR is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. They send a signal down the conductor and measure the time it takes for the signal, or part of the signal, to return.
VLAN - Virtual Local Area Network
A configuration of computers that acts as if all computers are con- nected by the same physical network but which may be located virtu- ally anywhere. DS00002761A-page 6

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 MDI/MDI−X Auto Crossover 3.4 Auto Negotiation 3.5 LINK MD® Cable Diagnostics 3.6 On-Chip Termination Resistors 3.7 Lookback Support 3.8 MAC (Media Access Controller) Block 3.9 Switch Block 3.10 IGMP Support 3.11 IPv6 MLD Snooping 3.12 Port Mirroring Support 3.13 IEEE 802.1Q VLAN Support 3.14 QoS Priority Support 3.15 Rate-Limiting Support 3.16 MAC Address Filtering Function 3.17 Queue Management Unit (QMU) 3.18 Device Clocks 3.19 Power 3.20 Internal Low Voltage LDO Regulator 3.21 Power Management 3.22 Wake-On-LAN 3.23 Interfaces 4.0 Register Descriptions 4.1 Device Registers 4.2 Register Map of CPU Accessible I/O Registers 4.3 Register Bit Definitions 4.4 Type-of-Service (TOS) Priority Control Registers 4.5 Indirect Access Data Registers 4.6 Power Management Control and Wake-Up Event Status 4.7 Go Sleep Time and Clock Tree Power-Down Control Registers 4.8 PHY and MII Basic Control Registers 4.9 Port 1 Control Registers 4.10 Port 2 Control Registers 4.11 Port 3 Control Registers 4.12 Switch Global Control Registers 4.13 Source Address Filtering Registers 4.14 TXQ Rate Control Registers 4.15 Auto-Negotiation Next Page Registers 4.16 EEE and Link Partner Advertisement Registers 4.17 Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 4.18 Host MAC Address Registers: MARL, MARM, and MARH 4.19 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) 4.20 Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) 4.21 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) 4.22 Management Information Base (MIB) Counters 4.23 Static MAC Address Table 4.24 Dynamic MAC Address Table 4.25 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read / Write Timing 7.2 Auto-Negotiation Timing 7.3 Serial EEPROM Interface Timing 7.4 Reset Timing and Power Sequencing 7.5 Reset Circuit Guidelines 7.6 Reference Circuits – LED Strap-In Pins 7.7 Reference Clock – Connection and Selection 8.0 Selection of Isolation Transformers 9.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service