Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 4
| 制造商 | Microchip |
| 描述 | IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII |
| 页数 / 页 | 213 / 4 — KSZ8463ML/RL/FML/FRL. Table of Contents |
| 文件格式/大小 | PDF / 2.4 Mb |
| 文件语言 | 英语 |
KSZ8463ML/RL/FML/FRL. Table of Contents
该数据表的模型线
文件文字版本
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KSZ8463ML/RL/FML/FRL Table of Contents
1.0 Introduction ... 5 2.0 Pin Description and Configuration ... 9 3.0 Functional Description ... 17 4.0 Register Descriptions .. 59 5.0 Operational Characteristics ... 189 6.0 Electrical Characteristics ... 190 7.0 Timing Specifications .. 193 8.0 Reference Clock: Connection and Selection ... 205 9.0 Selection of Isolation Transformers ... 206 10.0 Package Outline .. 207 Appendix A: Data Sheet Revision History ... 208 The Microchip Web Site .. 209 Customer Change Notification Service ... 209 Customer Support ... 209 Product Identification System .. 210 DS00002642A-page 4
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8463ML/RL/FML/FRL Table of Contents
1.0 Introduction ... 5 2.0 Pin Description and Configuration ... 9 3.0 Functional Description ... 17 4.0 Register Descriptions .. 59 5.0 Operational Characteristics ... 189 6.0 Electrical Characteristics ... 190 7.0 Timing Specifications .. 193 8.0 Reference Clock: Connection and Selection ... 205 9.0 Selection of Isolation Transformers ... 206 10.0 Package Outline .. 207 Appendix A: Data Sheet Revision History ... 208 The Microchip Web Site .. 209 Customer Change Notification Service ... 209 Customer Support ... 209 Product Identification System .. 210 DS00002642A-page 4
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service